Circuit-aware on-chip inductance extraction

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2001, Pages 245-248

  Hu, H ^a   Sapatnekar, S S ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT OSCILLATIONS; ELECTRIC RESISTANCE MEASUREMENT; INDUCTANCE MEASUREMENT; MICROPROCESSOR CHIPS;

INDUCTANCE COUPLINGS; INDUCTANCE MATRIX; ON CHIP INDUCTANCE EXTRACTION; OSCILLATION MAGNITUDE ERROR;

INTEGRATED CIRCUIT TESTING;

EID: 0034834937     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Inductance calculations in a coupled integrated circuit environment
2. Generating sparse inductance matrices with guaranteed stability
3. SPIE: Sparse partial inductance extraction
4. Return-limited inductances: A practical approach to on-chip inductance extraction
5. On chip inductance modeling and analysis
6. Multilevel metal capacitance models for CAD design synthesis systems
7. Challenges and opportunities for design innovations in nanometer technologies