Routabilty-driven repeater block planning for interconnect-centric floorplanning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 5, 2001, Pages 660-671

  Sarkar, Probir ^b,c   Koh, Cheng Kok ^a,b  

^a IEEE

^b PURDUE UNIVERSITY   (United States)

^c Conexant Systems ^*  (United States)

Author keywords

Buffer insertion; Deep submicrometer; Floorplanning; Physical design; Routing

Indexed keywords

ALGORITHMS; CONGESTION CONTROL (COMMUNICATION); ITERATIVE METHODS; MICROPROCESSOR CHIPS; ROUTERS;

BUFFER INSERTION;

TELECOMMUNICATION REPEATERS;

EID: 0035334418     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.920700     Document Type: Article

References (28)

1. Buffer block planning for interconnect-driven floorplanning
2. Performance optimization of VLSI interconnect layout
3. Buffer placement in distributed RC-tree networks for minimal Elmore delay
4. Optimal wire sizing and buffer insertion for low power and a generalized delay model
5. Interconnect layout optimization by simultaneous Steiner tree construction and buffer insertion
6. Closed form solution to simultaneous buffer insertion/sizing and wire sizing
7. Global wires harmful?
8. Interconnect delay estimation models for synthesis and design planning
9. Challenges and opportunities for design innovations in nanometer technologies
10. Floorplan design of VLSI circuits
11. Rectangle-packing-based module placement
12. Delay bounded buffered tree for timing driven floorplanning
13. Integrated floorplanning and interconnect planning
14. Routability-driven repeater block planning for interconnect-centric floorplanning
15. Interconnect design for deep submicron ICs
16. The transient response of damped linear networks with particular regard to wide-band amplifiers
17. Wire segmenting for improved buffer insertion
18. Graphs in floor-plan design
19. Partitioning by iterative deletion
20. A global router based on a multi commodity flow model
21. A detailed router based on incremental routing modifications: MIGHTY
22. A iterative-improvement penalty-function-driven wire routing system
23. Performance driven multi-layer general area routing for PCB/MCM designs
24. Relaxed simulated tempering for VLSI floorplan design