Testing of critical paths for delay faults

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 634-641

  Sharma, Manish ^a   Patel, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; LOGIC CIRCUITS; LOGIC GATES; THEOREM PROVING;

DELAY FAULTS;

INTEGRATED CIRCUIT TESTING;

EID: 0035683951     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. Model for delay faults based upon paths
2. Identification and test generation for primitive faults
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4. Resist: A recursive test pattern generation algorithm for path delay faults considering various test classes
5. Classification and identification of nonrobust untestable path delay faults
6. Synthesis of delay-verifiable combinational circuits
7. On delay fault testing in logic circuits
8. Fast identification of robust dependent path delay faults
9. Delay fault coverage and performance tradeoffs
10. Delay testing for non-robust untestable circuits
11. On path selection in combinational logic circuits
12. Efficient path selection for delay testing based on path clustering
13. Path selection for delay testing of deep sub-micron devices using statistical performance sensitivity analysis
14. Test generation for global delay faults
15. Enhancing delay defect coverage with path-segments
16. Robust and non-robust tests for path delay faults in a combinational circuit
17. On invalidation mechanisms for non-robust delay tests