Enhanced delay defect coverage with path-segments

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 385-392

  Sharma, Manish ^a   Patel, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; COMPUTER SIMULATION; GATES (TRANSISTOR); NAND CIRCUITS; SEQUENTIAL CIRCUITS;

DELAY FAULT TEST GENERATOR; PATH SEGMENTS;

INTEGRATED CIRCUIT TESTING;

EID: 0034482881     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)