Efficient path selection for delay testing based on path clustering

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 15, Issue 1, 1999, Pages 75-85

  Tani, Seiichiro ^a   Teramoto, Mitsuo ^a   Fukazawa, Tomoo ^a   Matsuhiro, Kazuyoshi ^a  

^a NTT Network Innovation Laboratories   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICE MODELS; VLSI CIRCUITS;

DELAY FAULT; DELAY TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0033312157     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008307516109     Document Type: Article

References (13)

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