Fedex - A fast bridging fault extractor

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 696-703

  Stanojevic, Zoran ^a   Walker, D M H ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC FAULT CURRENTS; MASKS; PARALLEL PROCESSING SYSTEMS;

BRIDGING FAULTS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0035680773     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. Resistive bridge fault modeling, simulation, and test generation
2. Computer-aided fault to defect mapping (CAFDM) for defecta diagnosis
3. VLASIC: A catastrophic fault yield simulator for integrated circuits
4. Hierarchical mapping of spot defects to catastrophic faults - Design and applications
5. Hierarchical extraction of critical area for shorts in very large ICs
6. Carafe: An inductive fault analysis tool for VLSI circuits
7. Realistic fault extraction for high-quality design and test of VLSI systems
8. A novel algorithm to extract two-node bridges
9. A scalable and efficient methodology to extract two node bridges from large industrial circuits
10. Extraction of critical areas for opens in large VLSI circuits
11. Critical area and fault probability prediction
12. Improvement in SRAM-based failure analysis using calibrated IDDQ testing
13. Critical area computation via voronoi diagrams
14. Bridging fault extraction from physical design data for manufacturing test development
15. ACE - A circuit extractor
16. POWER4 physical design