Realistic fault extraction for high-quality design and test of VLSI systems

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1997, Pages 29-37

  Goncalves, F M ^a   Teixeira, I C ^a   Teixeira, J P ^a  

^a INSTITUTO SUPERIOR TÉCNICO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER AIDED SOFTWARE ENGINEERING; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; PROBABILITY;

CRITICAL AREA EVALUATION; FAULT EXTRACTION; SLIDING WINDOW ALGORITHMS; SOFTWARE PACKAGE LOBS;

VLSI CIRCUITS;

EID: 0031340342     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (26)