Improvement of SRAM-based failure analysis using calibrated Iddq testing

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 130-136

  Balachandran, H ^a   Walker, D M H ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; DEFECTS; ELECTRIC CURRENTS; ERROR DETECTION; FAILURE ANALYSIS; MICROPROCESSOR CHIPS; NEURAL NETWORKS; PATTERN RECOGNITION; RANDOM ACCESS STORAGE;

BITMAP PATTERNS; CURRENT TESTING; FAULTY BITMAPS; VOLTAGE TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0029705861     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (26)