Critical area computation via Voronoi diagrams

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 46, Issue 3, 1999, Pages 463-474

  Papadopoulou, Evanthia ^a   Lee, D T ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; GRAPH THEORY; INTEGRATED CIRCUIT MANUFACTURE; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NUMERICAL METHODS; QUALITY CONTROL; VLSI CIRCUITS;

CRITICAL AREA; SHORTS; VERY LARGE SCALE INTEGRATION LAYOUT; VORONOI DIAGRAMS; YIELD PREDICTION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0032642992     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (20)