Bridging fault extraction from physical design data for manufacturing test development

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 760-769

  Stroud, Charles E ^a   Emmert, John M ^a   Bailey, James R ^b   Chhor, Khushru S ^c   Nikolic, Dragomir ^c  

^a University of North Carolina at Charlotte   (United States)

^b UNIVERSITY OF KENTUCKY   (United States)

^c CYPRESS SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER AIDED DESIGN; DATABASE SYSTEMS; INTEGRATED CIRCUIT MANUFACTURE; PROGRAMMABLE LOGIC CONTROLLERS; VLSI CIRCUITS;

COMPLEX PROGRAMMABLE LOGIC DEVICES; FAULT EXTRACTION; MANUFACTURING TEST DEVELOPMENT;

INTEGRATED CIRCUIT TESTING;

EID: 0034482515     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2000.894272     Document Type: Article

References (37)

1. M. Abramovici M. Breuer A. Friedman Digital System Testing and Testable Design 1990 IEEE Press NJ, Piscataway
2. W. Huang F. Lombardi An Approach to Testing Programmable/Configurable Field Programmable Gate Arrays Proc. IEEE VLSI Test Symp. 450 455 Proc. IEEE VLSI Test Symp. 1996
3. W. Huang F. Meyer X. Chen F. Lombardi Testing Configurable LUT-Based FPGAs IEEE Trans. on VLSI Systems 6 2 276 283 June 1998
4. T. Inoue S. Miyazaki H. Fujiwara Universal Fault Diagnosis for Lookup Table FPGAs IEEE Design & Test of Computers 15 1 39 44 Jan. 1998
5. C. Jordan W. Marnane Incoming Inspection of FPGAs Proc. European Test Conf. 371 377 Proc. European Test Conf. 1993
6. M. Renovell J. Figueras Y. Zorian Test of RAM-Based FPGA: Methodology and Application to Interconnects Proc. IEEE VLSI Test Symp. 230 237 Proc. IEEE VLSI Test Symp. 1997
7. M. Renovell J. Portal J. Figueras Y. Zorian Testing the Interconnect of RAM-Based FPGAs IEEE Design & Test of Computers 15 1 45 50 Jan. 1998
8. F. Lombardi D. Ashen X. Chen W. Huang Diagnosing Programmable Interconnect Systems for FPGAs Proc. ACM/SIGDA Intn'l Symp. on FPGAs 100 106 Proc. ACM/SIGDA Intn'l Symp. on FPGAs 1996
9. M. Renovell J. Portal J. Figueras Y. Zorian SRAM-based FPGA: Testing the LUT/RAM Modules Proc. IEEE Int'l. Test Conf. 1102 1111 Proc. IEEE Int'l. Test Conf. 1998
10. M. Renovell J. Portal J. Figueras Y. Zorian SRAM-based FPGA: Testing the Embedded RAM Modules J. of Electronic Testing: Theory and Application (JETTA) 14 1/2 159 167 1999
11. N. Shnidman W. Mangione-Smith M. Potkonjak On-line Fault Detection for Bus-Based Field Programmable Gate Arrays IEEE Trans. on VLSI Systems 6 4 656 666 Dec. 1998
12. S. Wang T. Tsai Test and Diagnosis of Faulty Logic Blocks in FPGAs Proc. IEEE Intn'l. Conf. on Computer Aided Design 722 727 Proc. IEEE Intn'l. Conf. on Computer Aided Design 1997
13. C. Stroud S. Konala P. Chen M. Abramovici Built-In Self-Test for Programmable Logic Blocks in FPGAs Proc. IEEE VLSI Test Symp. 387 392 Proc. IEEE VLSI Test Symp. 1996
14. C. Stroud E. Lee M. Abramovici BIST-based Diagnostics for FPGA Logic Blocks Proc. IEEE Int'l Test Conf. 539 547 Proc. IEEE Int'l Test Conf. 1997
15. C. Stroud S. Wijesuriya C. Hamilton M. Abramovici Built-In Self-Test of FPGA Interconnect Proc. Int'l. Test Conf. 404 411 Proc. Int'l. Test Conf. 1998
16. Cypress Programmable Logic: Delta 39K™ http://www.cypress.com/pld/delta39k.html
17. P. Maxwell R. Aitken L. Huismann The Effect on Quality of Non-Uniform fault Coverage and Fault Probability Proc. IEEE Int'l Test Conf. 739 746 Proc. IEEE Int'l Test Conf. 1994
18. C. Ouyang W. Maly Efficient Extraction of Critical Area in Large VLSI ICs Proc. Int'l Symp. Semiconductor Manufacturing 301 304 Proc. Int'l Symp. Semiconductor Manufacturing 1966
19. K. Mei Bridging and Stuck-At Faults IEEE Trans. on Computers c-23 7 720 727 1974
20. C. Timoc M. Buehler T. Griswold C. Pina F. Scott L. Hess Logical Models of Physical Failures Proc. IEEE Int'l Test Conf. 546 553 Proc. IEEE Int'l Test Conf. 1983
21. S. Ma I. Shaik R. Fetherston A Comparison of Bridging Fault Simulation Methods Proc. IEEE Int'l Test Conf. 587 595 Proc. IEEE Int'l Test Conf. 1999
22. J. Shen W. Maly J. Ferguson Inductive Fault Analysis of MOS Integrated Circuits IEEE Design and Test of Computers 2 13 26 1985
23. J. Ferguson A CMOS Fault Extractor for Inductive Fault Analysis IEEE Trans. on CAD 7 11 1181 1194 1988
24. A. Jee J. Ferguson Carafe: An Inductive Fault Analysis Tool for CMOS VLSI Circuits Proc. IEEE VLSI Test Symp. 92 98 Proc. IEEE VLSI Test Symp. 1993
25. J. Rearick J. Patel Fast and Accurate Bridging Fault Simulation Proc. IEEE Int'l Test Conf. 54 62 Proc. IEEE Int'l Test Conf. 1993
26. M. Abramovici P. Menon A Practical Approach to Fault Simulation and Test Generation for Bridging Faults IEEE Trans. on Computers 34 7 658 662 1985
27. C. Di J. Jess An Efficient CMOS Bridging Fault Simulator: With SPICE Accuracy IEEE Trans. on CAD 15 9 1071 1080 1996
28. S. Millman J. Garvey An Accurate Bridging Fault Test Pattern Generator Proc. IEEE Int'l Test Conf. 411 418 Proc. IEEE Int'l Test Conf. 1991
29. F. Ferguson T. Larrabee Test Pattern Generation for Realistic Bridge Faults in CMOS Ics Proc. IEEE Int'l Test Conf. 492 499 Proc. IEEE Int'l Test Conf. 1991
30. V. Sar-Dessai D. Walker Resistive Bridge Fault Modeling, Simulation, and Test Generation Proc. IEEE Int'l Test Conf. 596 605 Proc. IEEE Int'l Test Conf. 1999
31. Y. Liao D. Walker Optimal Voltage Testing for Physically-Based Faults Proc. IEEE VLSI Test Symp. 344 353 Proc. IEEE VLSI Test Symp. 1996
32. P. Maxwell R. Aitken Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds Proc. IEEE Int'l Test Conf. 63 72 Proc. IEEE Int'l Test Conf. 1993
33. M. Dalpasso M. Favalli P. Olivio B. Ricco Parametric Bridging Fault Characterization for Fault Simulation of Library Based Ics Proc. IEEE Int'l Test Conf. 486 495 Proc. IEEE Int'l Test Conf. 1992
34. D. Lavo B. Chess T. Larrabee F. Ferguson Diagnosing Realistic Bridging Faults with Single Stuck-At Information IEEE Trans. on CAD 17 3 255 267 1998
35. J. Emmert C. Stroud J. Bailey A New Bridging Fault Model for More Accurate Fault Behavior Proc. IEEE Automatic Test Conf. Proc. IEEE Automatic Test Conf. 2000
36. J. Bailey N Vocke C. Stroud N. Lau W. Orso C. Tran A Method for Testing Partially Programmable Logic Arrays in CPLDs Proc. IEEE Automatic Test Conf. Proc. IEEE Automatic Test Conf. 2000
37. C. Stroud C. Ryan Multiple Fault Simulation with Random and Clustered Fault Injection Proc. IEEE Int'l ASIC Conf. 218 221 Proc. IEEE Int'l ASIC Conf. 1995