DC power-bus modeling and design with a mixed-potential integral-equation formulation and circuit extraction

IEEE Transactions on Electromagnetic Compatibility

Volumn 43, Issue 4, 2001, Pages 426-436

  Fan, Jun ^a,b,c   Drewniak, James L ^a,b   Shi, Hao ^a,d   Knighten, James L ^a,c  

^a IEEE   (United States)

^b MISSOURI UNIVERSITY OF SCIENCE AND TECHNOLOGY   (United States)

^c NCR CORPORATION   (United States)

^d AGILENT TECHNOLOGIES   (United States)

Author keywords

Circuit extraction; dc power bus design; Dielectric losses; Mixed potential integral equation formulation; Segmented power plane; Surface mount decoupling

Indexed keywords

DIRECT CURRENT (DC) POWER BUS DESIGN; SEGMENTED POWER PLANE;

APPROXIMATION THEORY; BUSBARS; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; INTEGRAL EQUATIONS; MATHEMATICAL MODELS; MULTICHIP MODULES; PERMITTIVITY; PRINTED CIRCUIT BOARDS; SUBSTRATES; SURFACE MOUNT TECHNOLOGY;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035519365     PISSN: 00189375     EISSN: None     Source Type: Journal    
DOI: 10.1109/15.974622     Document Type: Article

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