Electrical linewidth test structures patterned in (100) silicon-on-insulator for use as CD standards

IEEE Transactions on Semiconductor Manufacturing

Volumn 14, Issue 4, 2001, Pages 356-364

  Cresswell, M W ^a,b   Bonevich, John E ^b   Allen, Richard A ^a,b   Guillaume, Nadine M P ^b,c   Giannuzzi, Lucille A ^d   Everist, Sarah C ^e   Murabito, Christine E ^b   Shea, Patrick J ^e   Linholm, Loren W ^a,b  

^a IEEE   (United States)

^b NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY   (United States)

^c GEORGE WASHINGTON UNIVERSITY   (United States)

^d UNIVERSITY OF CENTRAL FLORIDA   (United States)

^e SANDIA NATIONAL LABORATORIES   (United States)

Author keywords

BESOI; Cross bridge resistor; Electrical CD; HRTEM; Linewidth; SEM; Silicon micromachining; Silicon on insulator; Standards; Traceability

Indexed keywords

BONDED AND ETCHED BACK SILICON ON INSULATOR; CROSS BRIDGE RESISTORS; SILICON MICROMACHINING;

HIGH RESOLUTION ELECTRON MICROSCOPY; MICROMACHINING; RESISTORS; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DEVICE TESTING; STANDARDS; TRANSMISSION ELECTRON MICROSCOPY;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0035507963     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.964322     Document Type: Article

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