Modeling and analysis of semiconductor manufacturing systems with degraded behavior using Petri nets and Siphons

IEEE Transactions on Robotics and Automation

Volumn 17, Issue 5, 2001, Pages 576-588

  Jeng, Muder ^a,b   Xie, Xiaolan ^a,c  

^a IEEE   (Taiwan)

^b NATIONAL TAIWAN OCEAN UNIVERSITY   (Taiwan)

^c UNIVERSITÉ DE LORRAINE   (France)

Author keywords

Deadlock analysis; Degraded behavior; Petri nets; Semiconductor manufacturing; Siphons

Indexed keywords

DEADLOCK ANALYSIS; DEGRADED BEHAVIOR; SEMICONDUCTOR MANUFACTURING SYSTEMS;

CONSTRAINT THEORY; FINITE AUTOMATA; INTEGER PROGRAMMING; MATHEMATICAL MODELS; PHOTOLITHOGRAPHY; THEOREM PROVING;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0035485521     PISSN: 1042296X     EISSN: None     Source Type: Journal    
DOI: 10.1109/70.964659     Document Type: Article

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