A control method to reduce the standard deviation of flow time in wafer fabrication

IEEE Transactions on Semiconductor Manufacturing

Volumn 13, Issue 3, 2000, Pages 389-392

  Yoon, Hyun Joong ^a   Lee, Doo Yong ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Flow time (cycle time); Scheduling; Stochastic petri nets (SPN); Wafer fabrication

Indexed keywords

FAILURE (MECHANICAL); INTEGRATED CIRCUIT LAYOUT; MACHINERY; MATHEMATICAL MODELS; PETRI NETS; PROCESS CONTROL; RANDOM PROCESSES; SCHEDULING; SILICON WAFERS; THROUGHPUT;

FLOW TIME; OPERATION DUE DATE; STOCHASTIC PETRI NETS; WAFER FABRICATION;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0034250152     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.857950     Document Type: Article

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