-
3
-
-
0032308664
-
Formation of ultra-shallow junctions by ion implantation and RTA
-
Foad MA, Jennings D. Formation of ultra-shallow junctions by ion implantation and RTA. Solid State Technol 1998;41:43.
-
(1998)
Solid State Technol
, vol.41
, pp. 43
-
-
Foad, M.A.1
Jennings, D.2
-
4
-
-
84907884791
-
-
ESSDERC
-
Schmitz J, Tuinhout HP, Montree AH, Ponomarev YV, Stolk PA, Woerlee PH. Gate polysilicon optimization for deep-submicron MOSFETs. ESSDERC 1999, p. 156.
-
(1999)
Gate Polysilicon Optimization for Deep-submicron MOSFETs
, pp. 156
-
-
Schmitz, J.1
Tuinhout, H.P.2
Montree, A.H.3
Ponomarev, Y.V.4
Stolk, P.A.5
Woerlee, P.H.6
-
5
-
-
0031190685
-
Influence of the grain boundaries and intragrain defects on the performance of poly-Si thin film transistors
-
Morimoto Y., Jinno Y., Hirai K., Ogata H., Yamada T., Yoneda K. Influence of the grain boundaries and intragrain defects on the performance of poly-Si thin film transistors. J Electrochem Soc. 144(7):1997;2495.
-
(1997)
J Electrochem Soc
, vol.144
, Issue.7
, pp. 2495
-
-
Morimoto, Y.1
Jinno, Y.2
Hirai, K.3
Ogata, H.4
Yamada, T.5
Yoneda, K.6
-
6
-
-
0032116565
-
Dopant profile and defect control in ion implantation by RTA with high ramp-up rate
-
Saito S., Shishigushi S., Hamada K., Hayashi T. Dopant profile and defect control in ion implantation by RTA with high ramp-up rate. Mat Chem Phys. 54:1998;49.
-
(1998)
Mat Chem Phys
, vol.54
, pp. 49
-
-
Saito, S.1
Shishigushi, S.2
Hamada, K.3
Hayashi, T.4
-
7
-
-
0032116653
-
Ultra-shallow junction technology for 100 nm CMOS: XR LEAP implanter and RTP-centura rapid thermal annealer
-
Current M.I., Lopes D., Foad M., Boyd W. Ultra-shallow junction technology for 100. nm CMOS xR LEAP implanter and RTP-centura rapid thermal annealer Mat Chem Phys. 54:1998;33.
-
(1998)
Mat Chem Phys
, vol.54
, pp. 33
-
-
Current, M.I.1
Lopes, D.2
Foad, M.3
Boyd, W.4
-
8
-
-
84886448106
-
Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors
-
Tuinhout HP, Montree AH, Schmitz J, Stolk PA. Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors. IEDM Tech Digest 1997:631.
-
(1997)
IEDM Tech Digest
, pp. 631
-
-
Tuinhout, H.P.1
Montree, A.H.2
Schmitz, J.3
Stolk, P.A.4
-
9
-
-
0032096839
-
Gate engineering for deep-submicron CMOS transistors
-
Yu B., Ju D-.H., Lee W-.C., Kepler N., King T-.J., Hu C. Gate engineering for deep-submicron CMOS transistors. IEEE Trans Electron Dev. 45:1998;1253.
-
(1998)
IEEE Trans Electron Dev
, vol.45
, pp. 1253
-
-
Yu, B.1
Ju, D.-h.2
Lee, W.-c.3
Kepler, N.4
King, T.-j.5
Hu, C.6
-
10
-
-
0025474417
-
+ polysilicon gated PMOS devices
-
+ polysilicon gated PMOS devices. IEEE Trans Electron Dev. 37(8):1990;1842.
-
(1990)
IEEE Trans Electron Dev
, vol.37
, Issue.8
, pp. 1842
-
-
Pfiester, J.R.1
Baker, F.K.2
Mele, T.C.3
Tseng, H.-h.4
Tobin, P.J.5
Hayden, J.D.6
Miller, J.W.7
Gunderson, C.D.8
Parrillo, L.C.9
-
13
-
-
0001720449
-
Kinetics of arsenic segregation at grain boundaries in polycrystalline silicon
-
Nedelec S., Mathiot D. Kinetics of arsenic segregation at grain boundaries in polycrystalline silicon. Semicond Sci Technol. 12:1997;1438.
-
(1997)
Semicond Sci Technol
, vol.12
, pp. 1438
-
-
Nedelec, S.1
Mathiot, D.2
-
14
-
-
0342766514
-
-
TSUPREM_4, version 1998.4. Avant! Corporation, Fremont, CA
-
TSUPREM_4, version 1998.4. Avant! Corporation, Fremont, CA, 1998.
-
(1998)
-
-
|