Gate polysilicon optimization for deep-submicron MOSFETs

European Solid-State Device Research Conference

Volumn 13-15 Sept. 1999, Issue , 1999, Pages 156-159

  Schmitz, J ^a   Tuinhout, H P ^a   Montree, A H ^a   Ponomarev, Y V ^a   Stolk, P A ^a   Woerlee, P H ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DEPOSITION; MOS CAPACITORS; POLYSILICON; SEMICONDUCTING SILICON;

ACTIVATION TEMPERATURES; DEEP SUB-MICRON; DEPOSITION CONDITIONS; GATE DEPLETION; MOS GATES; MOS-FET; MOSFETS; POLYSILICON GATES;

MOSFET DEVICES;

EID: 84907884791     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. H. P. Tuinhout et al., IDM '97 p.631.
2. S. Shimizu et al., VLSI'97 p.107.