Formation of ultra-shallow junctions by ion implantation and RTA

Solid State Technology

Volumn 41, Issue 12, 1998, Pages 43-54

  Foad, Majeed A ^a   Jennings, Dean ^a,b  

^a APPLIED MATERIALS INC   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC RESISTANCE; ION IMPLANTATION; RAPID THERMAL ANNEALING; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DOPING;

ULTRA-SHALLOW JUNCTIONS;

SEMICONDUCTOR JUNCTIONS;

EID: 0032308664     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (10)

1. The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose CA, 1997.
2. S. Moffatt et al., "Electron-volt, High-current Implants into Silicon SDR (Surface Damage Region) and the Effects of Anneal Time to Form 200-700 Å, Low-leakage Junctions," presented at IIT98, Kyoto, Japan, 1998.
3. M.I. Current et al., "200 eV-10 keV Boron Implantation and Rapid Thermal Annealing: Secondary Ion Mass Spectroscopy and Transmission Electron Microscopy Study," J. Vac. Sci. Technol. B16, pp. 327-33, 1998.
4. M.A. Foad, J. England, S. Moffatt, D.G. Armour, Proc. 11th Int. Conf. on Ion Imp. Tech., 1996, IEEE, p. 603, 1997.
5. + Two-step Implantation," presented at IIT98, Kyoto, Japan, 1998.
6. + Ion Implantation Damage Characterization Using Rutherford Backscattering Spectrometry," presented at IIT98, Kyoto, Japan, 1998.
7. Private communication with M.J. Caturla, Lawrence Livermore National Lab, 1998.
8. S. Shishiguchi, A. Mineji, T. Hayashi, S. Saito, "Boron-implanted Shallow Junction Formation by High-temperature/Short-time/High-ramping Rate (400° C/1 sec) RTA," VLSI Technology Tech. Dig., p. 98, 1997.
9. J. Schmitz, "Design and Characterization of High-performance 0.13-μm NMOS devices," Essderc '96 Conference Proceedings, Bologna, Italy, p. 301, 1996.
10. E.J.H. Collart, A.J. Murrell et al., "Characterization of Low-energy Boron Implants and Electrical Results of Submicron PMOS Transistors," presented at IIT98, Kyoto, Japan, 1998.