Noise-tolerant dynamic circuit design technique

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 425-428

  Balamurugan, Ganesh ^a   Shanbhag, Naresh R ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; LOGIC CIRCUITS; LOGIC GATES; MOS DEVICES; SPURIOUS SIGNAL NOISE; THRESHOLD VOLTAGE;

DOMINO BUFFER; MULTIPLY ACCUMULATE CIRCUIT; NOISE TOLERANT DYNAMIC CIRCUIT; TWIN TRANSISTOR TECHNIQUE;

LOGIC DESIGN;

EID: 0033711830     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)