Application-driven processor design exploration for power-performance trade-off analysis

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 306-313

  Marculescu, Diana ^a   Iyer, Anoop ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; MICROPROCESSOR CHIPS; OPTIMIZATION; PROGRAM COMPILERS;

PROCESSOR DESIGN;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035212915     PISSN: 10923152     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCAD.2001.968638     Document Type: Article

References (39)

1. Reducing power in high-performance microprocessors
2. Power analysis of embedded software: A first step toward software power minimization
3. Saving power in the control path of embedded processors
4. Low-power design for real-time systems
5. Power analysis and minimization techniques for embedded DSP software
6. Modeling inter-instruction energy effects in a digital signal processor
7. Wattch: A framework for architectural-level power analysis and optimizations
8. Energy-driven integrated hardware-software optimizations using simplepower
9. Cycle-accurate simulation of energy consumption in embedded systems
10. Pipeline gating: Speculation control for energy reduction
11. System-level power consumption modeling and trade-off analysis techniques for superscalar processor design
12. Selective cache ways: On-demand cache resource allocation
13. The filter cache: An energy efficient memory structure
14. Code compression for low power embedded system design
15. Optimization of high-performance superscalar architectures for energy efficiency
16. Power efficient media processors: Design space exploration
17. Memory exploration for low power, embedded systems
18. Power optimization of variable voltage core-based systems
19. Energy minimization of system pipelines using multiple voltages
20. The simplescalar tool set, version 2.0
21. Register file design considerations in dynamically scheduled processors
22. An enhanced access and cycle time model for on-chip caches
23. A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization
24. MediaBench: A tool for evaluating and synthesizing multimedia and communication systems
25. A power estimation framework for designing low power portable video application
26. Low power circuit techniques
27. Datapath scheduling with multiple supply voltages and level converters
28. Extending value reuse to basic blocks with compiler support
29. Sequence compaction for power estimation: Theory and practice
30. Stratified random sampling for power estimation
31. Profile-driven generation of trace samples
32. Accuracy speed-up of parallel trace-driven architectural simulation
33. Representative traces for processor models with infinite cache
34. Microprocessor power estimation using profile-driven program synthesis