Extending value reuse to basic blocks with compiler support

IEEE Transactions on Computers

Volumn 49, Issue 4, 2000, Pages 331-347

  Huang, Jian ^a,b   Lilja, David J ^a,c  

^a IEEE   (United States)

^b SUN MICROSYSTEMS   (United States)

^c University of Minnesota   (United States)

Author keywords

Block history buffer; Block reuse; Compiler flow analysis; Value locality; Value reuse

Indexed keywords

EID: 0003202736     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.844346     Document Type: Article

References (21)

1. D. Burger, T. Austin, and S. Bennett, "The Simplescalar Tool Set, Version 2.0," Technical Report 1342, Computer Science Dept., Univ. of Wisconsin, Madison, June 1997.
2. M. Franklin, "Multiscalar Processors," PhD thesis, Univ. of Wisconsin, 1993.
3. A. Gonzalez and M. Valero, "Virtual Physical Registers," Proc. Fourth Int'l Symp. High Performance Computer Architecture (HPCA-4), pp. 175-184, Feb. 1998.
4. J. Huang and D. Lilja, "Exploiting Basic Block Value Locality with Block Reuse," Proc. Fifth Int'l Symp. High Performance Computer Architecture (HPCA-5), pp.106-114, Jan. 1999.
5. M. Lipasti, C. Wilkerson, and J. Shen, "Value Locality and Load Value Prediction," Proc. Eighth Int'l Conf. Architecture Support for Programming Languages and Operating Systems (ASPLOS VII), pp. 138-147, Oct. 1996.
6. M. Lipasti and J. Shen, "Exceeding the Dataflow Limit via Value Prediction," Proc. 29th Ann. ACM/IEEE Int'l Symp. Microarchitecture (MICRO-29), pp. 226-237, Dec. 1996.
7. M. Lipasti and J. Shen, "Superspeculative Microarchitecture for Beyond AD 2000," Computer, vol. 30, no. 9, pp. 59-66, Sept. 1997.
8. S. Melvin and Y. Patt, "Enhancing Instruction Scheduling with a Block-Structured ISA," Int'l J. Parallel Programming, vol. 23, no. 3, pp. 221-243, 1995.
9. S.S. Muchnick, Advanced Compiler Design and Implementation. Morgan Kaufmann, 1997.
10. K. Olukotun, B. Nayfeh, L. Hammond, K. Wilson, and K. Chang, "The Case for a Single-Chip Multiprocessor," Proc. Eighth Int'l Conf. Architecture Support for Programming Languages and Operating Systems (ASPLOS VII), pp. 2-11, Oct. 1996.
11. S. Richardson, "Caching Function Results: Faster Arithmetic by Avoiding Unnecessary Computation," Technical Report SMLI TR-92-1, Sun Microsystems Laboratories, Sept. 1992.
12. Y. Sazeides and J. Smith, "The Predictability of Data Values," Proc. 30th Ann. Int'l Symp. Microarchitecture (MICRO '30), pp. 248-258, Dec. 1997.
13. J. Smith and S. Vajapeyam, "Trace Processors: Moving to Fourth Generation Microarchitectures," Computer, vol. 30, no. 9, pp. 68-74, Sept. 1997.
14. A. Sodani and G. Sohi, "Dynamic Instruction Reuse," Proc. 24th Int'l Symp. Computer Architecture (ISCA), pp. 194-205, June 1997.
15. A. Sodani and G.S. Sohi, "An Empirical Analysis of Instruction Repetition," Proc. Eighth Int'l Symp. Architectural Support for Programming Languages and Operating Systems, pp. 35-45, Oct. 1998.
16. J. Steffan and T. Mowry, "The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization," Proc. Fourth Int'l Symp. High Performance Computer Architecture (HPCA-4), pp. 2-13, Feb. 1998.
17. J.-Y. Tsai, J. Huang, C. Amlo, D.J. Lilja, and P.-C. Yew, "The Superthreaded Processor Architecture," IEEE Trans. Computers, vol. 48, no. 9, pp. 881-902, Sept. 1999.
18. J.-Y. Tsai and P.-C. Yew, "Performance Study of a Concurrent Multithreaded Processor," Proc. Fourth Int'l Symp. High Performance Computer Architecture (HPCA-4), pp. 24-35, Feb. 1998.
19. G. Tyson and T. Austin, "Improving the Accuracy and Performance of Memory Communication through Renaming," Proc. 30th Ann. Int'l Symp. Microarchitecture (MICRO '30), pp. 218-227, Dec. 1997.
20. S. Vajapeyam and T. Mitra, "Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences," Proc. 24th Int'l Symp. Computer Architecture (ISCA), pp. 2-13, June 1997.
21. K. Wang and M. Franklin, "Highly Accurate Data Value Prediction Using Hybrid Predictors," Proc. 30th Ann. Int'l Symp. Microarchitecture (MICRO '30), pp. 281-290, Dec. 1997.