Simultaneous buffer and wire sizing for performance and power optimization

IEEE Symposium on Low Power Electronics

Volumn , Issue , 1996, Pages 271-276

  Cong, Jason ^a   Koh, Cheng Kok ^a   Leung, Kwok Shing ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY; POLYNOMIAL TIME ALGORITHMS; POWER DISSIPATION; POWER OPTIMIZATION; SIMULTANEOUS BUFFER AND WIRE SIZING;

ALGORITHMS; BUFFER CIRCUITS; ELECTRIC WIRE; ENERGY DISSIPATION; OPTIMIZATION; POLYNOMIALS; TIMING CIRCUITS; TRANSCEIVERS;

POWER ELECTRONICS;

EID: 0030402188     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)