Channel-based behavioral test synthesis for improved module reachability

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 283-288

  Makris, Yiorgos ^a   Orailoglu, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL STATE; GLOBAL DESIGN; PATH ANALYSIS; REACHABILITY; TEST SYNTHESIS;

EXHIBITIONS; REGRESSION ANALYSIS;

DESIGN;

EID: 0003285475     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761135     Document Type: Conference Paper

References (7)

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3. D. Gajski, N. Dutt, A. Wu, S. Lin, High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, 1992.
4. Y. Makris, A. Oiragolu, "RTL Test Justification and Propagation Analysis for Modular Designs", Journal of Electronic Testing: Theory & Applications, vol. 13, no. 2, pp. 105-120, 1998.
5. A. Orailoglu, I. G. Harris, "Microarchitectural Synthesis for Rapid BIST Testing", IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 16, no. 6, pp. 573-586, 1997.
6. P. Vishakantaiah, T. Thomas, J. A. Abraham, M. S. Abadir, "AMBIANT: Automatic Generation of Behavioral Modifications for Testability", ICCD, pp. 63-66, 1993.
7. K. Wagner, S. Dey, "High-Level Synthesis for Testability: A Survey and Perspective", 33rd DAC, pp. 131-136, 1996.