Behavioral Testability Insertion for Datapath/Controller Circuits

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 11, Issue 1, 1997, Pages 9-28

  Carletta, Joan E ^a,b,c   Papachristou, Christos A ^a,d,e,f  

^a Case Western Reserve University   (United States)

^b UNIVERSITY AT BUFFALO   (United States)

^c CASE WESTERN RESERVE UNIVERSITY   (United States)

^d UNIVERSITY OF CINCINNATI   (United States)

^e DREXEL UNIVERSITY   (United States)

^f JOHNS HOPKINS UNIVERSITY   (United States)

Author keywords

Behavioral testability analysis; BIST; Test synthesis

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; VLSI CIRCUITS;

BUILT IN SELF TEST (BIST); DESIGN FOR TESTABILITY (DFT);

INTEGRATED CIRCUIT TESTING;

EID: 0031212493     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008291616071     Document Type: Article

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