Breaking correlation to improve testability

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 75-80

  Ockunzzi, K ^a   Papachristou, C ^a  

^a Case Western Reserve University   (United States)

Author keywords

BIST; DFT; Test synthesis

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; CORRELATION METHODS; DATA FLOW ANALYSIS; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; MONTE CARLO METHODS; PROBABILITY DISTRIBUTIONS;

CONTROL DATA FLOW GRAPH; REGISTER TRANSFER LEVEL; TEST SYNTHESIS;

BUILT-IN SELF TEST;

EID: 0035004976     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

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13. TAO: Regular expression based high-level testability analysis and optimization
14. Partial BIST insertion to eliminate data correlation