Testability Enhancement for Control-Flow Intensive Behaviors

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 13, Issue 3, 1998, Pages 239-257

  Ockunzzi, Kelly A ^a,b   Papachristou, Christos A ^a,c,d,e,f  

^a Case Western Reserve University   (United States)

^b CASE WESTERN RESERVE UNIVERSITY   (United States)

^c UNIVERSITY OF CINCINNATI   (United States)

^d DREXEL UNIVERSITY   (United States)

^e JOHNS HOPKINS UNIVERSITY   (United States)

^f IEEE   (United States)

Author keywords

Behavioral testability analysis and insertion; BIST; Test synthesis

Indexed keywords

BUILT-IN SELF TEST; PROBABILITY; VLSI CIRCUITS;

BEHAVIORAL TESTABILITY; TEST SYNTHESIS;

INTEGRATED CIRCUIT TESTING;

EID: 0032289894     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008381718989     Document Type: Article

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