The 2nd Order Analysis of IDDQ Test Data

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn Part F5373300, Issue , 2000, Pages 376-384

  Li, Shengli ^a   Zhang, Kai ^a   Lo, Jien Chung ^a  

^a University of Rhode Island   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT SIGNATURES; DEEP SUB-MICRON; DEEP-SUB MICRONS; DELTA-I; ORDER ANALYSIS; SEMATECH; TEST DATA; TESTING DATA; VARIANCE INFORMATION;

DIES; INTEGRATED CIRCUIT TESTING;

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; VLSI CIRCUITS;

DIE SELECTION; ONLINE TESTING;

EID: 0034515695     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2000.887178     Document Type: Conference Paper

References (12)

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