Testing the local interconnect resources of SRAM-based FPGA's

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 16, Issue 5, 2000, Pages 513-520

  Renovell, M ^a   Portal, J M ^a   Figueras, J ^b   Zorian, Y ^c  

^a LIRMM   (France)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c LogicVision Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; FIELD PROGRAMMABLE GATE ARRAYS; INTERCONNECTION NETWORKS; INTERFACES (COMPUTER); MULTIPLEXING EQUIPMENT; RANDOM ACCESS STORAGE; SHIFT REGISTERS; VLSI CIRCUITS;

CONFIGURABLE INTERFACE MODULES; CONFIGURABLE INTERFACE MULTIPLEXERS; LOCAL INTERCONNECT RESOURCES; STATIC RANDOM ACCESS MEMORY (SRAM);

INTEGRATED CIRCUIT TESTING;

EID: 0034298301     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008376917755     Document Type: Article

References (21)

1. S.D. Brown, R.J. Francis, J. Rose, and S.G. Vranesic, Field-Programmable Gate Arrays, Kluwer Academic Publishers, 1992.
2. S.M. Trimberger (Ed.), Field-Programmable Gate Array Technology, Kluwer Academic Publishers, 1994.
3. C. Jordan and W.P. Marnane, "Incoming Inspection of FPGAs," Proc. of IEEE European Test Conference, 1993, pp. 371-377.
4. M. Renovell, J. Figueras, and Y. Zorian, "Test of RAM-Based FPGA: Methodology and Application to the Interconnect," Proc. 15th IEEE VLSI Test Symposium, Monterey, CA, USA, May 1997, pp. 230-237.
5. M. Renovell, J.M. Portal, J. Figueras, and Y. Zorian, "Test Pattern and Test Generation Methodology for the Logic of RAM-Based FPGA," Proc. IEEE Asian Test Symposium, Akita, Japan, Nov. 1997, pp. 254-259.
6. M. Renovell, J.M. Portal, J. Figueras, and Y Zorian, "Testing the Configurable Logic of RAM-based FPGA," Proc. IEEE Int. Conf. on Design, Automation and Test in Europe, Paris, France, Feb. 1998, pp. 82-88.
7. M. Renovell, J.M. Portal, J. Figueras, and Y Zorian, "Testing the Interconnect of RAM-Based FPGAs," IEEE Design & Test of Computer, Special Issue on FPGAs, Jan-March 1998, vol. 15, no. 1, pp. 45-50.
8. T. Inoue, H. Fujiwara, H. Michinishi, T. Yokohira, and T. Okamoto, "Universal Test Complexity of Field-Programmable Gate Arrays," Proc. 4th Asian Test Symposium, Bangalora, India, Nov. 1995, pp. 259-265.
9. H. Michinishi, T. Yokohira, T. Okamoto, T. Inoue, and H. Fujiwara, "A Test Methodology for Interconnect Structures of LUT-based FPGAs," Proc. IEEE 5th Asian Test Symposium, Nov. 1996, pp. 68-74.
10. H. Michinishi, T. Yokohira, T. Okamoto, T. Inoue, and H. Fujiwara, "Testing for the Programming Circuits of LUT-based FPGAs," Proc. IEEE 6th Asian Test Symposium, November 1997, pp. 242-247.
11. T. Inoue, S. Miyazaki, and H. Fujiwara, "Universal Fault Diagnosis for Lookup Table FPGAs," IEEE Design & Test of Computer, Special Issue on FPGAs, Jan.-March 1998, vol. 15, no. 1, pp. 39-44.
12. M. Abramovici and C. Stroud, "No-Overhead BIST for FPGAs," Proc. 1st IEEE International On-line Testing Workshop, Nice, France, 1995, pp. 90-92.
13. C. Stroud, P. Chen, S. Konala, and M. Abramovici, "Evaluation of FPGA Resources for Built-In Self Test of Programmable Logic Blocks," Proc. of 4th ACM/SIGDA Int. Symposium on FPGAs, 1996, pp. 107-113.
14. M. Abramovici and C. Stroud, "ILA BIST for FPGAs: A Free Lunch with Gourmet Food," Proc. 2nd IEEE International On-line Testing Workshop, Biarritz, France, 1996, pp. 91-95.
15. W.K. Huang and F. Lombardi, "An Approach for Testing Programmable/Configurable Field Programmable Gate Arrays," Proc. 14th IEEE VLSI Test Symposium, Princeton, NJ, USA, May 1996, pp. 450-455.
16. F. Lombardi, D. Ashen, X.T. Chen, and W.K. Huang, "Diagnosing Programmable Interconnect Systems for FPGAs," FPGA '96, Monterey, CA, USA, 1996, pp. 100-106.
17. D.G. Ashen, F.J. Meyer, N. Park, and F. Lombardi, "Testing of Programmable Logic Devices (PLD) with Faulty Resources," IEEE International Workshop on Defect & Tolerance in VLSI Systems, Paris, Oct. 1997, pp. 76-84.
18. W.K. Huang, F.J. Meyer, N. Park, and F. Lombardi, "Testing Memory Modules in SRAM-based Configurable FPGAs," IEEE International Workshop on Memory Technology, Design and Test, Aug., 1997.
19. M. Hermann and W. Hoffmann, "Fault Modeling and Test Generation for FPGAs," in Lecture Notes in Computer Science, Field Programmable Logic, R.W. Hartenstein and M.Z. Servit (Eds.), Springer-Verlag, 1994, pp. 1-10.
20. R.O. Durate and M. Nicolaidis, "A Test Methodology Applied to Cellular Logic Programmable Gate Arrays," in Lecture Notes in Computer Science, Field Programmable Logic, R.W. Hartenstein and M.Z. Servit (Eds.), Springer-Verlag, 1994, pp. 11-22.
21. Xilinx, The Programmable Logic Data Book, San Jose, USA, 1994.