Test pattern and test configuration generation methodology for the logic of RAM-based FPGA

Proceedings of the Asian Test Symposium

Volumn , Issue , 1997, Pages 254-259

  Renovell, M ^a   Portal, J M ^a   Figueras, J ^a   Zorian, Y ^a  

^a LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

LOGIC GATES; MATHEMATICAL MODELS; RANDOM ACCESS STORAGE; TABLE LOOKUP;

LOGIC CIRCUITS;

EID: 0031362435     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

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