Testing of programmable logic devices (PLD) with faulty resources

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1997, Pages 76-84

  Ashen, D G ^a   Meyer, F J ^a   Park, N ^a   Lombardi, F ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUIT TESTING; SEMICONDUCTOR DEVICE MODELS;

PROGRAMMABLE LOGIC DEVICES (PLD);

LOGIC DEVICES;

EID: 0031333685     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1997.628312     Document Type: Conference Paper

References (10)

1. A. Hassan J. Rajski V. K. Agrawal Testing and Diagnosis of Interconnects using Boundary-scan International Test Conference 126 137 International Test Conference 1985
2. W. H. Kautz Testing for Fault in Wiring Networks IEEE Transactions on Computers C-23 4 358 363 1974
3. C. Stroud P. Chen S. Konala M. Abramovici Evaluation of FPGA Resources for BIST of Programmable Logic Blocks Proc. 4th ACM/SIGDA Int. Symp. on FPGAs 107 113 Proc. 4th ACM/SIGDA Int. Symp. on FPGAs 1996
4. T. Liu W. K. Huang F. Lombardi Testing of Uncustomized Segmented Channel FPGAs Proc. ACM Int. Symp. on FPGAs 125 131 Proc. ACM Int. Symp. on FPGAs 1995
5. Programmable Gate Array Data Book 1991 Xilinx Inc. San Jose
6. F. Lombardi D. Ashen X. T. Chen W. K. Huang Diagnosing Programmable Interconnect Systems for FPGAs Proc. ACM International Symposium on FPGAs 100 106 Proc. ACM International Symposium on FPGAs Monterey 1996-February
7. E. J. Mc Cluskey Logic Design Principles: With Emphasis on Testable Semicustoms Circuits 1986 Prentice-Hall N.J., Englewood Cliffs
8. Altera Data Book 1993 San Jose
9. W. K. Huang F. Lombardi A General Technique for Testing FPGAs Proc. IEEE VLSI Test Symposium 450 455 Proc. IEEE VLSI Test Symposium Princeton 1996-May
10. S. Brown R.J. Francis J. Rose Z.G. Vranesic Field Programmable Gate Arrays 1992 Kluwer Academic Publishers Mass, Boston