Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 5, 2000, Pages 633-636

  Chakrabarty, Krishnendu ^a   Murray, Brian T ^b   Iyengar, Vikram ^a  

^a Duke University   (United States)

^b DELPHI CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; FINITE AUTOMATA; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; NAND CIRCUITS; ROM; SHIFT REGISTERS;

BUILT-IN TEST PATTERN GENERATION; SLOW TESTERS; TEST PER CLOCK BUILT-IN SELF TEST; TWISTED RING COUNTERS;

BUILT-IN SELF TEST;

EID: 0034289979     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.894170     Document Type: Article

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