-
1
-
-
25844483149
-
COM (Cost Oriented Memory) Testing
-
Baltimore, Sept.
-
T. Yamada, A. Fujiwara, and M. Inoue, "COM (Cost Oriented Memory) Testing," Proc. International Test Conference, Baltimore, Sept. 1992, p. 259.
-
(1992)
Proc. International Test Conference
, pp. 259
-
-
Yamada, T.1
Fujiwara, A.2
Inoue, M.3
-
2
-
-
0022874110
-
Memory Chip Test Economics
-
Washington, Sept.
-
A. Tuszynski, "Memory Chip Test Economics," Proc. International Test Conference, Washington, Sept. 1986, pp. 190-194.
-
(1986)
Proc. International Test Conference
, pp. 190-194
-
-
Tuszynski, A.1
-
4
-
-
0022794746
-
Built-In Self-Testing of Embedded Memories
-
Oct.
-
S.K. Jain and S.H. Stroud. "Built-In Self-Testing of Embedded Memories," IEEE Design and Test of Computer, Vol. 3, No. 5, pp. 27-37, Oct. 1986.
-
(1986)
IEEE Design and Test of Computer
, vol.3
, Issue.5
, pp. 27-37
-
-
Jain, S.K.1
Stroud, S.H.2
-
6
-
-
0022915125
-
A Novel Approach for Testing Memories Using a Built-in Self Testing Technique
-
Washington, Sept.
-
K.T. Le and K.K. Saluja, "A Novel Approach for Testing Memories Using a Built-in Self Testing Technique," Proc. International Test Conference, Washington, Sept. 1986, pp. 830-838.
-
(1986)
Proc. International Test Conference
, pp. 830-838
-
-
Le, K.T.1
Saluja, K.K.2
-
7
-
-
0024124138
-
Fault Modeling and Test Algorithm Development for Static Random Access Memories
-
Washington, Sept.
-
R. Dekker, F. Beenker, and L. Thijssen, "Fault Modeling and Test Algorithm Development for Static Random Access Memories," Proc. International Text Conference, Washington, Sept. 1988, pp. 343-352.
-
(1988)
Proc. International Text Conference
, pp. 343-352
-
-
Dekker, R.1
Beenker, F.2
Thijssen, L.3
-
8
-
-
0027609172
-
Failure Analysis of High-Density CMOS SRAMs
-
June
-
S. Nair, F. Agricola, and W. Maly, "Failure Analysis of High-Density CMOS SRAMs," IEEE Design and Test of Computer, Vol. 10, No. 2, pp. 13-23, June 1993.
-
(1993)
IEEE Design and Test of Computer
, vol.10
, Issue.2
, pp. 13-23
-
-
Nair, S.1
Agricola, F.2
Maly, W.3
-
9
-
-
0025399890
-
An Overview of Deterministic Functional RAM Chip Testing
-
March
-
A.J. Van de Goor and C.A. Verruijt, "An Overview of Deterministic Functional RAM Chip Testing," ACM Computing Surveys, Vol. 22, No. 1, March 1990.
-
(1990)
ACM Computing Surveys
, vol.22
, Issue.1
-
-
Van De Goor, A.J.1
Verruijt, C.A.2
-
11
-
-
0016470497
-
Detection of Pattern-Sensitive Faults in Random-Access Memories
-
J.P. Hayes, "Detection of Pattern-Sensitive Faults in Random-Access Memories," IEEE Transactions on Computers, Vol. C-24, No. 2, pp. 150-157, 1975.
-
(1975)
IEEE Transactions on Computers
, vol.C-24
, Issue.2
, pp. 150-157
-
-
Hayes, J.P.1
-
12
-
-
25844470917
-
Exact Aliasing Computation And/Or Aliasing Free Design for RAM BIST
-
San Jose, Aug.
-
V.N. Yarmolik and M. Nicolaidis, "Exact Aliasing Computation And/Or Aliasing Free Design for RAM BIST," Proc. of Workshop on Memory Testing, San Jose, Aug. 1993.
-
(1993)
Proc. of Workshop on Memory Testing
-
-
Yarmolik, V.N.1
Nicolaidis, M.2
-
13
-
-
0017982899
-
Efficient Algorithms for Testing Semiconductor Random-Access Memories
-
June
-
C. Nair, S.M. Thatte, and J.A. Abraham, "Efficient Algorithms for Testing Semiconductor Random-Access Memories," IEEE Transactions on Computers, Vol. C-27, pp. 572-576, June 1978.
-
(1978)
IEEE Transactions on Computers
, vol.C-27
, pp. 572-576
-
-
Nair, C.1
Thatte, S.M.2
Abraham, J.A.3
-
14
-
-
0019689426
-
A March Test for Functional Faults in Semiconductor Random-Access Memories
-
D.S. Suk and S.M. Reddy, "A March Test for Functional Faults in Semiconductor Random-Access Memories," IEEE Transactions on Computers, Vol. C-30, No. 12, pp. 982-985, 1981.
-
(1981)
IEEE Transactions on Computers
, vol.C-30
, Issue.12
, pp. 982-985
-
-
Suk, D.S.1
Reddy, S.M.2
-
15
-
-
0020278451
-
Simple and Efficient Algorithm for Functional RAM Testing
-
M. Marinescu, "Simple and Efficient Algorithm for Functional RAM Testing," Proc. International Test Conference, 1982, pp. 236-239.
-
(1982)
Proc. International Test Conference
, pp. 236-239
-
-
Marinescu, M.1
-
16
-
-
0022012145
-
An Improved Method for Detecting Functional Faults in Random-Access Memories
-
C.A. Papachristou and N.B. Saghal, "An Improved Method for Detecting Functional Faults in Random-Access Memories," IEEE Transactions on Computers, Vol. C-34, No. 2, pp. 110-116, 1985.
-
(1985)
IEEE Transactions on Computers
, vol.C-34
, Issue.2
, pp. 110-116
-
-
Papachristou, C.A.1
Saghal, N.B.2
-
18
-
-
0028553067
-
A Transparent Built-In Self-Test Scheme for Detecting Single V-Coupling Faults in RAMs
-
San Jose, CA, Aug. 8-9
-
B.F. Cockburn, "A Transparent Built-In Self-Test Scheme for Detecting Single V-Coupling Faults in RAMs," IEEE International Workshop on Memory Technology Design and Testing, San Jose, CA, Aug. 8-9, 1994, pp. 119-124.
-
(1994)
IEEE International Workshop on Memory Technology Design and Testing
, pp. 119-124
-
-
Cockburn, B.F.1
-
19
-
-
0024915815
-
Testing for Coupled Cells in Random-Access Memories
-
Washington, Aug.
-
J. Savir, W.H. McAnney, and S.R. Vecchio, "Testing for Coupled Cells in Random-Access Memories," Proc. International Test Conference, Washington, Aug. 1989, pp. 439-451.
-
(1989)
Proc. International Test Conference
, pp. 439-451
-
-
Savir, J.1
McAnney, W.H.2
Vecchio, S.R.3
-
20
-
-
0020708314
-
Exhaustive Generation of Bit Pattern with Application to VLSI Self-Testing
-
Z. Barzilai, D. Coppersmith, and A. Rosenberg, "Exhaustive Generation of Bit Pattern with Application to VLSI Self-Testing," IEEE Transactions on Computers, Vol. C-31, No. 2, pp. 190-194, 1983.
-
(1983)
IEEE Transactions on Computers
, vol.C-31
, Issue.2
, pp. 190-194
-
-
Barzilai, Z.1
Coppersmith, D.2
Rosenberg, A.3
-
21
-
-
0021385453
-
Iterative Exhaustive Pattern Generation for Logic Testing
-
D.T. Tang and C.L. Chen, "Iterative Exhaustive Pattern Generation for Logic Testing," IBM J. Res. Develop., Vol. 28, No. 2, pp. 212-219, 1984.
-
(1984)
IBM J. Res. Develop.
, vol.28
, Issue.2
, pp. 212-219
-
-
Tang, D.T.1
Chen, C.L.2
-
23
-
-
0000319342
-
Covering Arrays and Intersecting Codes
-
N.J.A. Sloane, "Covering Arrays and Intersecting Codes," J. Combinatorial Design, Vol. 1, No. 1, pp. 51-64, 1993.
-
(1993)
J. Combinatorial Design
, vol.1
, Issue.1
, pp. 51-64
-
-
Sloane, N.J.A.1
-
24
-
-
0000391239
-
Explicit Construction of Exponential Sized Families of k-independent sets
-
N. Alon, "Explicit Construction of Exponential Sized Families of k-independent sets," Discrete Math., Vol. 58, pp. 191-193, 1986.
-
(1986)
Discrete Math.
, vol.58
, pp. 191-193
-
-
Alon, N.1
-
25
-
-
27144442020
-
-
Tech. Rep. 84D005, Ecole Nationale Superieure des Telecom, Dec.
-
P. Busschbach, "Constructive Methods to Solve the Problem of: s-surjectivity, Conflict Resolution, Coding in Defective Memories," Tech. Rep. 84D005, Ecole Nationale Superieure des Telecom, Dec. 1984.
-
(1984)
Constructive Methods to Solve the Problem Of: S-surjectivity, Conflict Resolution, Coding in Defective Memories
-
-
Busschbach, P.1
-
26
-
-
0020929233
-
Exhaustive Test Pattern Generation with Constant Weight Vectors
-
D.T. Tang and C.L. Woo, "Exhaustive Test Pattern Generation with Constant Weight Vectors," IEEE Transactions on Computers, Vol. C-22, No. 12, pp. 1145-1150, 1983.
-
(1983)
IEEE Transactions on Computers
, vol.C-22
, Issue.12
, pp. 1145-1150
-
-
Tang, D.T.1
Woo, C.L.2
-
27
-
-
25844488617
-
Exhaustive Testing of Combinatorial Circuits
-
2
-
G. Cohen, P. Godlewski, and M.G. Karpovsky, "Exhaustive Testing of Combinatorial Circuits," Traitement du signal, revue scientifique francaise publiee par le GRETSI, Vol. 1, No. 2-2, pp. 224-226, 1984.
-
(1984)
Traitement du Signal, Revue Scientifique Francaise Publiee par le GRETSI
, vol.1
, Issue.2
, pp. 224-226
-
-
Cohen, G.1
Godlewski, P.2
Karpovsky, M.G.3
-
28
-
-
2342468575
-
Exhaustive Testing of Almost all Devices with Outputs Depending on Limited Number of Inputs
-
L.B. Levitin and M.G. Karpovsky, "Exhaustive Testing of Almost all Devices with Outputs Depending on Limited Number of Inputs," Open Systems & Information Dynamics, Vol. 2, No. 3, pp. 1-16, 1994.
-
(1994)
Open Systems & Information Dynamics
, vol.2
, Issue.3
, pp. 1-16
-
-
Levitin, L.B.1
Karpovsky, M.G.2
-
29
-
-
11644300129
-
Multimoding and Its Suppression in Twisted Ring Counters
-
Nov.
-
W. Bleickardt, "Multimoding and Its Suppression in Twisted Ring Counters," The Bell System Technical Journal, pp. 2029-2050, Nov. 1968.
-
(1968)
The Bell System Technical Journal
, pp. 2029-2050
-
-
Bleickardt, W.1
-
30
-
-
0028582549
-
Transparent Memory BIST
-
San Jose, CA, Aug. 8-9
-
M.G. Karpovsky and V.N. Yarmolik, "Transparent Memory BIST," IEEE International Workshop on Memory Technology Design and Testing, San Jose, CA, Aug. 8-9, 1994, pp. 106-111.
-
(1994)
IEEE International Workshop on Memory Technology Design and Testing
, pp. 106-111
-
-
Karpovsky, M.G.1
Yarmolik, V.N.2
-
31
-
-
0041149867
-
Transparent Memory Testing for Pattern Sensitive Faults
-
Washington, Oct.
-
M.G. Karpovsky and V.N. Yarmolik, "Transparent Memory Testing for Pattern Sensitive Faults," Proc. International Test Conference, Washington, Oct. 1994, pp. 368-377.
-
(1994)
Proc. International Test Conference
, pp. 368-377
-
-
Karpovsky, M.G.1
Yarmolik, V.N.2
-
32
-
-
0003972145
-
-
John Wiley and Sons, New York
-
P.H. Bardell, W.H. McAnney, and J. Savier, Built-in Test for VLSI: Pseudorandom Techniques, John Wiley and Sons, New York, 1987.
-
(1987)
Built-in Test for VLSI: Pseudorandom Techniques
-
-
Bardell, P.H.1
McAnney, W.H.2
Savier, J.3
-
33
-
-
0025480955
-
A Multiple Seed Linear Feedback Shift Register
-
Washington, Sept.
-
J. Savir and W.H. McAnney, "A Multiple Seed Linear Feedback Shift Register," Proc. International Test Conference, Washington, Sept. 1990, pp. 657-659.
-
(1990)
Proc. International Test Conference
, pp. 657-659
-
-
Savir, J.1
McAnney, W.H.2
-
34
-
-
0028744431
-
Efficient UBIST for RAMs
-
April
-
M. Nicolaidis, "Efficient UBIST for RAMs," VLSI Test Symposium, April 1994, pp. 158-166.
-
(1994)
VLSI Test Symposium
, pp. 158-166
-
-
Nicolaidis, M.1
-
35
-
-
0024915815
-
Testing for Coupled Cells in Random-Access Memories
-
Washington, Sept.
-
J. Savir et al., "Testing for Coupled Cells in Random-Access Memories," Proc. International Test Conference, Washington, Sept. 1989, pp. 439-451.
-
(1989)
Proc. International Test Conference
, pp. 439-451
-
-
Savir, J.1
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