-
1
-
-
0003597645
-
-
M. Soderstrand, M. A. W. Jenkins, G. Jullien, and F. Taylor, Eds., Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. Piscataway, NJ: IEEE Press, 1986.
-
Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. Piscataway, NJ: IEEE Press, 1986.
-
-
Soderstrand, M.1
Jenkins, M.A.W.2
Jullien, G.3
Taylor, F.4
-
3
-
-
33749900199
-
Practical realization of mod
-
vol. 16, pp. 466167, June 1980.
-
A. S. Ramnarayan Practical realization of mod p, p prime multiplier," Electron. Lett., vol. 16, pp. 466167, June 1980.
-
P, P Prime Multiplier," Electron. Lett.
-
-
Ramnarayan, A.S.1
-
4
-
-
0019008835
-
A high-speed low-cost modulo P, multiplier with RNS arithmetic application,"
-
vol. 68, pp. 529-532, Apr. 1980.
-
M. Soderstrand and C. Vernia A high-speed low-cost modulo P, multiplier with RNS arithmetic application," Proc. IEEE, vol. 68, pp. 529-532, Apr. 1980.
-
Proc. IEEE
-
-
Soderstrand, M.1
Vernia, C.2
-
5
-
-
0019069143
-
Implementation of multiplication, modulo a prime number, with applications to theoretic transforms,"
-
29, pp. 899-905, Oct. 1980.
-
G. A. Jullien Implementation of multiplication, modulo a prime number, with applications to theoretic transforms," IEEE Trans. Comput., vol. C-29, pp. 899-905, Oct. 1980.
-
IEEE Trans. Comput., Vol. C
-
-
Jullien, G.A.1
-
6
-
-
0019592222
-
Large moduli multipliers for signal processing,"
-
28, pp. 731-736, July 1981.
-
F. J. Taylor Large moduli multipliers for signal processing," IEEE Trans. Circuits Syst., vol. CAS-28, pp. 731-736, July 1981.
-
IEEE Trans. Circuits Syst., Vol. CAS
-
-
Taylor, F.J.1
-
7
-
-
0020139085
-
A VLSI residue arithmetic multiplier,"
-
31, pp. 540-546, June 1982.
-
F. J. Taylor A VLSI residue arithmetic multiplier," IEEE Trans. Comput., vol. C-31, pp. 540-546, June 1982.
-
IEEE Trans. Comput., Vol. C
-
-
Taylor, F.J.1
-
8
-
-
0020114805
-
An autoscale residue multiplier,"
-
31, pp. 321-325, Apr. 1982.
-
F. J. Taylor and Huang An autoscale residue multiplier," IEEE Trans. Comput., vol. C-31, pp. 321-325, Apr. 1982.
-
IEEE Trans. Comput., Vol. C
-
-
Taylor, F.J.1
Huang2
-
9
-
-
33749905753
-
A memoryless mod (2" ±1) residue multiplier,"
-
vol. 28, pp. 414-115, Jan. 1991.
-
A. Hiasat A memoryless mod (2" ±1) residue multiplier," Electron. Lett., vol. 28, pp. 414-115, Jan. 1991.
-
Electron. Lett.
-
-
Hiasat, A.1
-
10
-
-
0028515598
-
Residue multipliers using factored decomposition,"
-
vol. 41, pp. 623-627, Sept. 1994.
-
M. Dugdale Residue multipliers using factored decomposition," IEEE Trans. Circuits Syst. II, vol. 41, pp. 623-627, Sept. 1994.
-
IEEE Trans. Circuits Syst. II
-
-
Dugdale, M.1
-
11
-
-
0030371386
-
Semi-custom VLSI design for RNS multipliers using combinational logic approach," in
-
3rd IEEE Int. Conf. Electronics, Circuits and Systems (ICECS'96), vol. 2, Oct. 1996, pp. 935-938.
-
A. Hiasat Semi-custom VLSI design for RNS multipliers using combinational logic approach," in Proc. 3rd IEEE Int. Conf. Electronics, Circuits and Systems (ICECS'96), vol. 2, Oct. 1996, pp. 935-938.
-
Proc.
-
-
Hiasat, A.1
-
12
-
-
0026679901
-
Novel approaches to the design of VLSI RNS multipliers,"
-
vol. 39, pp. 52-57, Jan. 1992.
-
D. Radhakrishnan and Y. Yuan Novel approaches to the design of VLSI RNS multipliers," IEEE Trans. Circuits Syst. //, vol. 39, pp. 52-57, Jan. 1992.
-
IEEE Trans. Circuits Syst.
-
-
Radhakrishnan, D.1
Yuan, Y.2
-
13
-
-
0026188738
-
A VLSI modulo m multiplier,"
-
vol. 40, pp. 873-878, July 1991.
-
G. Alia and E. Martinelli A VLSI modulo m multiplier," IEEE Trans. Comput., vol. 40, pp. 873-878, July 1991.
-
IEEE Trans. Comput.
-
-
Alia, G.1
Martinelli, E.2
-
14
-
-
0029308383
-
Fast combinatorial RNS processors for DSP applications,"
-
vol. 44, pp. 624-633, May 1995.
-
E. Di Claudio, F. Piazza, and G. Orlandi Fast combinatorial RNS processors for DSP applications," IEEE Trans. Comput., vol. 44, pp. 624-633, May 1995.
-
IEEE Trans. Comput.
-
-
Di Claudio, E.1
Piazza, F.2
Orlandi, G.3
-
15
-
-
0033893444
-
New efficient structure for a modular multiplier for RNS,"
-
vol. 49, pp. 170-174, Feb. 2000.
-
A. Hiasat New efficient structure for a modular multiplier for RNS," IEEE Trans. Comput., vol. 49, pp. 170-174, Feb. 2000.
-
IEEE Trans. Comput.
-
-
Hiasat, A.1
-
16
-
-
0029405986
-
A systolic architecture for modulo multiplication,"
-
vol. 42, pp. 725-729, Sept. 1995.
-
K. Elleithy and M. Bayoumi A systolic architecture for modulo multiplication," IEEE Trans. Circuits Syst. II, vol. 42, pp. 725-729, Sept. 1995.
-
IEEE Trans. Circuits Syst. II
-
-
Elleithy, K.1
Bayoumi, M.2
-
17
-
-
0028320347
-
Design of residue generators and multioperand modular adders using carry-save adders,"
-
vol. 43, pp. 68-77, Jan. 1994.
-
S. Piestrak Design of residue generators and multioperand modular adders using carry-save adders," IEEE Trans. Comput., vol. 43, pp. 68-77, Jan. 1994.
-
IEEE Trans. Comput.
-
-
Piestrak, S.1
-
18
-
-
0025635450
-
Improved cellular structures for bit-steered ROM finite ring systolic arrays," in
-
1990, pp. 1414-1417.
-
G. Jullien and W. Miller Improved cellular structures for bit-steered ROM finite ring systolic arrays," in Proc. IEEE Int. Symp. Circuits and Systems, New Orleans, LA, 1990, pp. 1414-1417.
-
Proc. IEEE Int. Symp. Circuits and Systems, New Orleans, la
-
-
Jullien, G.1
Miller, W.2
-
20
-
-
0032000038
-
Residue-to-binary arithmetic converter for the moduli set (2fc, 2fc -1, 2fc- ' -1 ),"
-
vol. 45, pp. 204-209, Feb. 1998.
-
A. Hiasat and H. Abdel-Aty-Zohdy Residue-to-binary arithmetic converter for the moduli set (2fc, 2fc -1, 2fc- ' -1 )," IEEE Trans. Circuits Syst. II, vol. 45, pp. 204-209, Feb. 1998.
-
IEEE Trans. Circuits Syst. II
-
-
Hiasat, A.1
Abdel-Aty-Zohdy, H.2
-
21
-
-
0026852363
-
Fast and flexible architectures for RNS arithmetic decoding,"
-
vol. 39, pp. 226-235, Apr. 1992.
-
K. Elleithy and M. Bayoumi Fast and flexible architectures for RNS arithmetic decoding," IEEE Trans. Circuits Syst. II, vol. 39, pp. 226-235, Apr. 1992.
-
IEEE Trans. Circuits Syst. II
-
-
Elleithy, K.1
Bayoumi, M.2
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