A vlsi residue arithmetic multiplier

IEEE Transactions on Computers

Volumn C-31, Issue 6, 1982, Pages 540-546

  Taylor, Fred J ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

Author keywords

Modular arithmetic; multiplication; residue arithmetic

Indexed keywords

INTEGRATED CIRCUITS - VERY LARGE SCALE INTEGRATION;

COMPUTERS, DIGITAL;

EID: 0020139085     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1982.1676036     Document Type: Article

References (8)

1. W. K. Jenkins and F. J. Leon, “The use of residue number system in the design of finite impulse response filters,” IEEE Trans. Circuits Syst., vol. CAS-24, Apr. 1977.
2. G. A. Jullien, “Residue number scaling and other operations using ROM arrays,” IEEE Trans. Comput., vol. C-27, pp. 325–337, Apr. 1978.
3. C. H. Huang and F. J. Taylor, “Memory compression scheme for modular arithmetic,” IEEE Trans. Acoust., Speech, Signal Processing, to be published.
4. M. A. Soderstrand, “A high speed low-cost recursive filter using residue arithmetic,” Proc. IEEE, vol. 65, July 1977.
5. N. S. Szabo and R. I. Tanaka, Residue Arithmetic and Its Applications To Computer Technology. New York: McGraw-Hill, 1967.
6. W. J. Jenkins, “A highly efficient residue-combinatorial architecture for digital filters,” Proc. IEEE, vol. 66, pp. 700–702, June 1978.
7. M. A. Soderstrand and C. Vernia, “A high-speed low-cost modulo pimultiplier with RNS arithmetic applications,” Proc. IEEE, vol. 68, pp. 527–532, Apr. 1980.
8. G. Bioul, M. Davio, and J. J. Quisquarter, “A computation scheme for an adder modulo (2n – 1),” Digital Process., no. 1, pp. 309–318, 1975.