Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders

IEEE Transactions on Computers

Volumn 43, Issue 1, 1994, Pages 68-77

  Piestrak, Stanislaw J ^a  

^a WROCLAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

Addition modulo A; arithmetic codes; binary ; carry save adders; Chinese remainder theorem; generator modulo A; modular arithmetic; multioperand modular addition; residue arithmetic; residue generators; residue number system (RNS); to residue number system converter

Indexed keywords

ADDERS; ROM;

HIGH-SPEED RESIDUE-TO-BINARY CONVERTER; MULTIOPERAND MODULAR ADDER; N-INPUT RESIDUE GENERATORS; VLSI IMPLEMENTATION;

VLSI CIRCUITS;

EID: 0028320347     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.250610     Document Type: Article

References (23)

1. A. Avizienis, “A set of algorithms for a diagnosable arithmetic unit,” Tech. Rep. 32-546, Jet Propulsion Lab., Calif. Inst. Technol., Pasadena, CA, Mar. 1 964.
2. A. Aviâžienis “Arithmetic codes: Cost and effectiveness studies for applications in digital system design,” IEEE Trans. Comput., vol. C-20, pp. 1322-1331, Nov. 1971.
3. J. F. Wakerly, Error Detecting Codes, Self-Checking Circuits and Applications. New York: North-Holland, 1978.
4. S. J. Piestrak, “Self-testing checkers for arithmetic codes with any check base A in Proc. 1991 Pacific Rim Int. Symp. Fault-Tolerant Syst., Kawasaki, Japan, Sept. 26-27, 1991, pp. 162-167.
5. V. Piuri, M. Berzieri, A. Bisaschi, and A. Fabi, “Residue arithmetic for a fault-tolerant multiplier: The choice of the best triple of bases,” Microproc. and Microprogr., vol. 20, pp. 15-23, 1988.
6. T. J. Siegel and R. J. Veracca, “Design and performance of the IBM Enterprise System/9000 Type 9121 vector facility,” IBM J. Res. Develop., vol. 35, pp. 367-381, May 1991.
7. S. R. Barraclough et al., “The design and implementation of the IMS A110 image and signal processor,” in Proc. IEEE Custom lntegr. Circuits Conf, 1989, pp. 24.5.1-24.5.4.
8. M. A. Soderstrand, “A new hardware implementation of modulo adders for reside number systems,” in Proc. 26th Midwest Symp. Circuits Systems, 1983, pp. 412-415.
9. N. S. Szabo and R. I. Tanaka, Residue Arithmetic and its Applications to Computer Technology. New York: McGraw-Hill, 1967.
10. M. A. Soderstrand et al., Eds., Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. New York: IEEE Press, 1986.
11. W. K. Jenkins and B. J. Leon, “The use of residue number system in the design of finite impulse response filters,” IEEE Trans. Circuits Syst., vol. CAS-24, pp. 191-201, Apr. 1977.
12. M. Taheri, G. A. Jullien, and W. C. Miller, “High-speed signal processing using systolic arrays over finite rings,” IEEE J. Selected Areas Commun., vol. 6, pp. 504-512, Apr. 1988.
13. C. N. Zhang, G. A. Jullien, and W. C. Miller, “Recursive reduction in finite ring computations,” in Proc. Conf Rec. 23th Asilomar Conf Circs., Systs, Comput., 1989, pp. 854-857.
14. C. N. Zhang, G. A. Jullien, and W. C. Miller, “A neural-like network approach to finite ring computations,” IEEE Trans. Circuits Syst., vol. 37, pp. 1048-1052, Aug. 1990.
15. R. M. Capocelli and R. Giancarlo, “Efficient VLSI networks for converting an integer from binary system to residue number system and vice versa,” IEEE Trans. Circuits Syst., vol. CAS-35, pp. 1425-1430, Nov. 1988.
16. G. Alia and E. Martinelli, “VLSI binary-residue converters for pipeline processing,” Comput. J., vol. 33, pp. 473-475, no. 5, 1990.
17. K. Hwang, Computer Arithmetic: Principle, Architecture ad Design. New York: Wiley, 1979.
18. C. N. Zhang, B. Shirazi, and D. Y.Y. Yun, “Parallel designs for Chinese remainder conversion,” in Proc. Int. Conf Parallel Processing, Aug. 17-21, 1987, pp. 557-559.
19. L. Skavantzos, “Design of multi-operand carry-save adders for arith-metic modulo (2 n +1),” Electron. Lett, vol. 25, no. 17, pp. 1152-1153, Aug. 17, 1989.
20. C. K. Koc and C. Y. Hung, “Multi-operand modulo addition using carry save adders,” Electron. Lett., vol. 26, no. 6, pp. 361-363, Mar. 15, 1990.
21. K. P. Lee, M. A. Bayoumi, and K. M. Elleithy, “A fast and flexible residue decoder based on the Chinese Remainder Theorem,” in Proc. ISCAS’89, 1989, pp. 200-203.
22. K. M. Elleithy, M. A. Bayoumi, and K. P. Lee, “θ( logN) architectures for RNS arithmetic decoding,” in Proc. 9th Int. Symp. Comput. Arithm., Santa Monica, CA, Sept. 3-6, 1989, pp. 202-209.
23. I. S. Reed et al., “VLSI implementation of GSC architecture with a new ripple carry adder,” in Proc. ICCD’88, 1988, pp. 520-523.