Fast Combinatorial RNS Processors for DSP Applications

IEEE Transactions on Computers

Volumn 44, Issue 5, 1995, Pages 624-633

  Claudio, Elio D Di ^a   Piazza, Francesco ^b   Orlandi, Gianni ^a  

^a SAPIENZA UNIVERSITY OF ROME   (Italy)

^b UNIVERSITÀ POLITECNICA DELLE MARCHE   (Italy)

Author keywords

Binary multipliers; digital signal processing; mixed radix arithmetic; parallel architectures; pseudo residue; residue number system; systolic arrays; VLSI processors

Indexed keywords

BINARY MULTIPLIERS; CHINESE REMAINDER THEOREM; MIXED RADIX ARITHMETIC; PSEUDO RESIDUE; RESIDUE NUMBER SYSTEMS;

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; LARGE SCALE SYSTEMS; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; SYSTOLIC ARRAYS; TABLE LOOKUP; VLSI CIRCUITS;

MULTIPLYING CIRCUITS;

EID: 0029308383     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.381948     Document Type: Article

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