Large Moduli Multipliers for Signal Processing

IEEE Transactions on Circuits and Systems

Volumn 28, Issue 7, 1981, Pages 731-736

  Taylor, Fredrick J ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FILTERS, DIGITAL;

SIGNAL PROCESSING;

EID: 0019592222     PISSN: 00984094     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCS.1981.1085027     Document Type: Article

References (13)

1. G. A. Jullien, “Residue number scaling and other operations using ROM arrays,” IEEE Trans. Comput., vol. C-27, pp. 325–337, Apr. 1978.
2. C. H. Huang and F. J. Taylor, “Memory compression scheme for modular arithmetic, IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-27, Dec. 1979.
3. M. A. Soderstrand, “A high speed low-cost recursive filter using residue arithmetic,” Proc. IEEE, vol. 65, July 1977.
4. N. S. Szabo and R. I. Tanaka, Residue Arithmetic and Its Applications to Computer Technology. New York: McGraw-Hill, 1967.
5. W. K. Jenkins and B. J. Leon, “The use of residue number system in the design of finite impulse response filters,” IEEE Trans. Circuits Syst., vol. CAS-24, Apr. 1977.
6. W. K. Jenkins, “Techniques for residue-to-analog conversion for residue-encoded digital filters,” IEEE Trans. Circuits Syst., vol. CAS-25, July 1978.
7. A. Peled and B. Liu, “A new hardware realization of digital filters,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-22, Dec. 1974.
8. W. J. Jenkins, “A highly efficient residue-combinatorial architecture for digital filters,” Proc. IEEE, vol. 66, pp. 700–702, June 1978.
9. J. M. Pollard, “Implementation of number-theoretic transforms,” Electron. Lett., vol. 12, no. 22, pp. 378–379, July 1976.
10. H. Nussbaumer, “Digital filters using read-only memories,” Electron. Lett. vol. 11, pp. 294–295, 1976.
11. M. A. and E. L. Fields, “Multiplier for residue-number-arithmetic digital filters,” Electron. Lett., vol. 13, no. 6, Mar. 17, 1977.
12. G. Bioul, M. Davio, and J. J. Quisquarter, “A computation scheme for an adder modulo (2 n —1),” Digital Process, Georgi Publisher, Switzerland, no. 1, pp. 309–318, 1975.
13. M. A. Soderstrand and C. Vernia, “A high-speed low-cost modulo Pi multiplier with RNS arithmetic applications,” Proc. IEEE, vol. 68, pp. 527–532, Apr. 1980.