Test Set Compaction for Combinational Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 14, Issue 11, 1995, Pages 1370-1378

  Chang, Jau Shien ^a   Lin, Chen Shang ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; CONSTRAINT THEORY; ERROR DETECTION; HEURISTIC METHODS; MODIFICATION; OPTIMIZATION;

ESSENTIAL FAULT PRUNING; FORCED PAIR MERGING; POST GENERATION COMPACTION; TEST SET COMPACTION;

COMBINATORIAL CIRCUITS;

EID: 0029406001     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.469663     Document Type: Article

References (16)

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