Cost-effective generation of minimal test sets for stuck at faults in combinational logic circuits

Proceedings - Design Automation Conference

Volumn , Issue , 1993, Pages 102-106

  Kajihara, Seiji ^a   Pomeranz, Irith ^a   Kinoshita, Kozo ^a   Reddy, Sudhakar M ^a  

^a OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COST ACCOUNTING; HEURISTIC PROGRAMMING;

MINIMAL TEST SETS; STUCK AT FAULTS;

INTEGRATED CIRCUIT TESTING;

EID: 0027150951     PISSN: 01467123     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)