On compacting test sets by addition and removal of test vectors

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1994, Pages 202-207

  Kajihara, Seiji ^a   Pomeranz, Irith ^a   Kinoshita, Kozo ^a   Reddy, Sudhakar M ^a  

^a OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FAULT CURRENTS; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; VECTORS;

DYNAMIC COMPACTION; TEST VECTORS;

COMBINATORIAL CIRCUITS;

EID: 0028745067     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)