-
1
-
-
0024908745
-
-
8, pp. 1247-1266, Dec. 1989.
-
R. Harjani, R.A. Rutenbar, and L. R. Carley, "OASYS: A framework for analog circuit synthesis," IEEE Trans. Computer-Aided Design, vol. 8, pp. 1247-1266, Dec. 1989.
-
R.A. Rutenbar, and L. R. Carley, "OASYS: a Framework for Analog Circuit Synthesis," IEEE Trans. Computer-Aided Design, Vol.
-
-
Harjani, R.1
-
2
-
-
33749926053
-
-
1C scenarios for the 90's," in VLSI Symp., 1995.
-
P.R. Gray, "Possible analog 1C scenarios for the 90's," in VLSI Symp., 1995.
-
"Possible Analog
-
-
Gray, P.R.1
-
3
-
-
0029719538
-
-
1996, pp. 298-303.
-
L.R. Carley, G. G. E. Gielen, R. A. Rutenbar, and W. M. C. Sansen, "Synthesis tools for mixed-signal ICs: Progress on frontend and backend strategies," in Proc. IEEE/ACM Design Automation Conf., June 1996, pp. 298-303.
-
G. G. E. Gielen, R. A. Rutenbar, and W. M. C. Sansen, "Synthesis Tools for Mixed-signal ICs: Progress on Frontend and Backend Strategies," in Proc. IEEE/ACM Design Automation Conf., June
-
-
Carley, L.R.1
-
4
-
-
0030107342
-
-
15, pp. 273-294, Mar. 1996.
-
E.S. Ochotta, R. A. Rutenbar, and L. R. Carley, "Synthesis of high performance analog circuits in ASTRX/OBLX," IEEE Trans. ComputerAided Design, vol. 15, pp. 273-294, Mar. 1996.
-
R. A. Rutenbar, and L. R. Carley, "Synthesis of High Performance Analog Circuits in ASTRX/OBLX," IEEE Trans. ComputerAided Design, Vol.
-
-
Ochotta, E.S.1
-
5
-
-
0029547474
-
-
14, pp. 1557-1568, Dec. 1995.
-
K. Krishna and S.W. Director, "The linearized performance penalty (LPP) method for optimization of parametric yield and its reliability," IEEE Trans. Computer-Aided Design, vol. 14, pp. 1557-1568, Dec. 1995.
-
And S.W. Director, "The Linearized Performance Penalty (LPP) Method for Optimization of Parametric Yield and Its Reliability," IEEE Trans. Computer-Aided Design, Vol.
-
-
Krishna, K.1
-
6
-
-
33749926705
-
-
215. Berlin, Germany: Springer-Verlag, 1983.
-
A.V. Fiacco and K. O. Kortanek, Eds., Semi-Infinite Programming and Applications, ser. Lecture Notes in Economics and Mathematical Systems 215. Berlin, Germany: Springer-Verlag, 1983.
-
And K. O. Kortanek, Eds., Semi-Infinite Programming and Applications, Ser. Lecture Notes in Economics and Mathematical Systems
-
-
Fiacco, A.V.1
-
7
-
-
26444479778
-
-
220, no. 4598, pp. 671-680, May 1983.
-
S. Kirkpatrick, C.D. Gelatt, and M. P. Vecchi, "Optimization by simulated annealing," Science, vol. 220, no. 4598, pp. 671-680, May 1983.
-
C.D. Gelatt, and M. P. Vecchi, "Optimization by Simulated Annealing," Science, Vol.
-
-
Kirkpatrick, S.1
-
8
-
-
0028727533
-
-
1994, pp. 586-593.
-
T. Mukherjee, L.R. Carley, and R. A. Rutenbar, "Synthesis of manufacturable analog circuits," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1994, pp. 586-593.
-
L.R. Carley, and R. A. Rutenbar, "Synthesis of Manufacturable Analog Circuits," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov.
-
-
Mukherjee, T.1
-
9
-
-
79959613887
-
-
55, pp. 1929-1939, Dec. 1967.
-
R.A. Rohrer, "Fully automated network design by digital computer, preliminary considerations," Proc. IEEE, vol. 55, pp. 1929-1939, Dec. 1967.
-
"Fully Automated Network Design by Digital Computer, Preliminary Considerations," Proc. IEEE, Vol.
-
-
Rohrer, R.A.1
-
10
-
-
85176670582
-
-
14, pp. 401-4112, Apr. 1995.
-
P.C. Maulik, L. R. Carley, and R. A. Rutenbar, "Integer programming-based topology selection of cell-level analog circuits," IEEE Trans. Computer-Aided Design, vol. 14, pp. 401-4112, Apr. 1995.
-
L. R. Carley, and R. A. Rutenbar, "Integer Programming-based Topology Selection of Cell-level Analog Circuits," IEEE Trans. Computer-Aided Design, Vol.
-
-
Maulik, P.C.1
-
11
-
-
0023994941
-
-
7, pp. 501-518, Apr. 1988.
-
W. Nye, D.C. Riley, A. Sangiovanni-Vincentelli, and A. L. Tits, "DELIGHT.SPICE: An optimization-based system for design of integrated circuits," IEEE Trans. Computer-Aided Design, vol. 7, pp. 501-518, Apr. 1988.
-
D.C. Riley, A. Sangiovanni-Vincentelli, and A. L. Tits, "DELIGHT.SPICE: an Optimization-based System for Design of Integrated Circuits," IEEE Trans. Computer-Aided Design, Vol.
-
-
Nye, W.1
-
12
-
-
0024681330
-
-
24, pp. 659-672, June 1989.
-
M.G. R. DeGrauwe, B. L. A. G. Goffart, C. Meixenberger, M. L. A. Pierre, J. B. Litsios, J. Rijmenants, O. J. A. P. Nys, E. Dijkstra, B. Joss, M. K. C. M. Meyvaert, T. R. Schwarz, and M. D. Pardoen, "Toward an analog system design environment," IEEE J. Solid-State Circuits, vol. 24, pp. 659-672, June 1989.
-
DeGrauwe, B. L. A. G. Goffart, C. Meixenberger, M. L. A. Pierre, J. B. Litsios, J. Rijmenants, O. J. A. P. Nys, E. Dijkstra, B. Joss, M. K. C. M. Meyvaert, T. R. Schwarz, and M. D. Pardoen, "Toward an Analog System Design Environment," IEEE J. Solid-State Circuits, Vol.
-
-
-
13
-
-
0025448791
-
-
25, pp. 707-713, June 1990.
-
G.E. Gielen, H. C. Walscharts, and W. C. Sansen, "Analog circuit design optimization based on symbolic simulation and simulated annealing," IEEE]. Solid-State Circuits, vol. 25, pp. 707-713, June 1990.
-
H. C. Walscharts, and W. C. Sansen, "Analog Circuit Design Optimization Based on Symbolic Simulation and Simulated Annealing," IEEE. Solid-State Circuits, Vol.
-
-
Gielen, G.E.1
-
14
-
-
0025383839
-
-
9, Feb. 1990.
-
H.Y. Koh, C. H. Sequin, and P. R. Gray, "OPASYN: A compiler for MOS operational amplifiers," IEEE Trans. Computer-Aided Design, vol. 9, Feb. 1990.
-
C. H. Sequin, and P. R. Gray, "OPASYN: a Compiler for MOS Operational Amplifiers," IEEE Trans. Computer-Aided Design, Vol.
-
-
Koh, H.Y.1
-
15
-
-
0026946787
-
-
11, pp. 1402-1418, Nov. 1992.
-
J.P. Harvey, M. I. Elmasry, and B. Leung, "STAIC: An interactive framework for synthesizing CMOS and BiCMOS analog circuits," IEEE Trans. Computer-Aided Design, vol. 11, pp. 1402-1418, Nov. 1992.
-
M. I. Elmasry, and B. Leung, "STAIC: an Interactive Framework for Synthesizing CMOS and BiCMOS Analog Circuits," IEEE Trans. Computer-Aided Design, Vol.
-
-
Harvey, J.P.1
-
16
-
-
33749916316
-
-
1992, pp. 129-143.
-
E.S. Ochotta, R. A. Rutenbar, and L. R. Carley, "Equation-free synthesis of high-performance linear analog circuits," in Proc. Joint Brown/MIT Conf. Advanced Research in VLSI and Parallel Systems, Providence, RI, Mar. 1992, pp. 129-143.
-
R. A. Rutenbar, and L. R. Carley, "Equation-free Synthesis of High-performance Linear Analog Circuits," in Proc. Joint Brown/MIT Conf. Advanced Research in VLSI and Parallel Systems, Providence, RI, Mar.
-
-
Ochotta, E.S.1
-
20
-
-
33749932685
-
-
1993, pp. 18.1/1-8.
-
V. Raghavan, R.A. Rohrer, M. M. Alaybeyi, J. E. Bracken, J. Y. Lee, and L. T Pillage, "AWE inspired," in Proc. IEEE Custom Integrated Circuit Conf., May 1993, pp. 18.1/1-8.
-
R.A. Rohrer, M. M. Alaybeyi, J. E. Bracken, J. Y. Lee, and L. T Pillage, "AWE Inspired," in Proc. IEEE Custom Integrated Circuit Conf., May
-
-
Raghavan, V.1
-
21
-
-
3042903096
-
-
15. Berlin, Germany: Springer-Verlag, 1979.
-
R. Heittich, Ed., Semi-Infinite Programming, ser. Lecture Notes in Control and Information Sciences 15. Berlin, Germany: Springer-Verlag, 1979.
-
Ed., Semi-Infinite Programming, Ser. Lecture Notes in Control and Information Sciences
-
-
Heittich, R.1
-
22
-
-
84870042024
-
-
3.1/1-8, May 1992.
-
S.W. Director, P. Feldmann, and K. Krishna, "Optimization of parametric yield: A tutorial," Proc. IEEE Custom Integrated Circuit Conf., pp. 3.1/1-8, May 1992.
-
P. Feldmann, and K. Krishna, "Optimization of Parametric Yield: a Tutorial," Proc. IEEE Custom Integrated Circuit Conf., Pp.
-
-
Director, S.W.1
-
23
-
-
0027872091
-
-
12, pp. 1868-1879, Dec. 1993.
-
P. Feldmann and S.W. Director, "Integrated circuit quality optimization using surface integrals," IEEE Trans. Computer-Aided Design, vol. 12, pp. 1868-1879, Dec. 1993.
-
And S.W. Director, "Integrated Circuit Quality Optimization Using Surface Integrals," IEEE Trans. Computer-Aided Design, Vol.
-
-
Feldmann, P.1
-
24
-
-
0024029576
-
-
7, pp. 645-658, June 1988.
-
D.E. Hocevar, P. F Cox, and P. Yang, "Parametric yield optimization for MOS circuit blocks," IEEE Trans. Computer-Aided Design, vol. 7, pp. 645-658, June 1988.
-
P. F Cox, and P. Yang, "Parametric Yield Optimization for MOS Circuit Blocks," IEEE Trans. Computer-Aided Design, Vol.
-
-
Hocevar, D.E.1
-
25
-
-
0022597953
-
-
1C yield optimization based on fundamental fabrication parameters," IEEE Trans. Computer-Aided Design, vol. 5, Jan. 1996.
-
M.A. Styblinski and L. J. Opalski, "Algorithms and software tools of 1C yield optimization based on fundamental fabrication parameters," IEEE Trans. Computer-Aided Design, vol. 5, Jan. 1996.
-
And L. J. Opalski, "Algorithms and Software Tools of
-
-
Styblinski, M.A.1
-
26
-
-
0028256775
-
-
13, pp. 57-71, Jan. 1994.
-
K.J. Antriech, H. E. Graeb, and C. U. Wieser, "Circuit analysis and optimization driven by worst case distances," IEEE Trans. ComputerAided Design, vol. 13, pp. 57-71, Jan. 1994.
-
H. E. Graeb, and C. U. Wieser, "Circuit Analysis and Optimization Driven by Worst Case Distances," IEEE Trans. ComputerAided Design, Vol.
-
-
Antriech, K.J.1
-
28
-
-
84945715056
-
-
471-478, Feb. 1985.
-
P. Cox, P. Yang, S.S. Mahant-Shetti, and P. Chatterjee, "Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits," IEEE Trans. Electron Devices, vol. ED-32, pp. 471-478, Feb. 1985.
-
P. Yang, S.S. Mahant-Shetti, and P. Chatterjee, "Statistical Modeling for Efficient Parametric Yield Estimation of MOS VLSI Circuits," IEEE Trans. Electron Devices, Vol. ED-32, Pp.
-
-
Cox, P.1
-
30
-
-
0021202647
-
-
1C fabrication process simulator," IEEE Trans. Computer-Aided Design, vol. CAD-3, pp. 20-46, Jan. 1984.
-
S.R. Nassif, A. J. Strojwas, and S. W. Director, "FABRICS II: A statistically based 1C fabrication process simulator," IEEE Trans. Computer-Aided Design, vol. CAD-3, pp. 20-46, Jan. 1984.
-
A. J. Strojwas, and S. W. Director, "FABRICS II: a Statistically Based
-
-
Nassif, S.R.1
-
33
-
-
0023314734
-
-
29, pp. 21-89, 1987.
-
E. Polak, "On mathematical foundations of nondifferentiable optimization in engineering design," SI AM Rev., vol. 29, pp. 21-89, 1987.
-
"On Mathematical Foundations of Nondifferentiable Optimization in Engineering Design," SI AM Rev., Vol.
-
-
Polak, E.1
-
34
-
-
0020912186
-
-
22nd IEEE Conf. Decision and Control, Dec. 1983, pp. 410-411.
-
H. Parsa and A.L. Tits, "Nonuniform, dynamically adapted discretization for functional constraints in engineering design problems," in Proc. 22nd IEEE Conf. Decision and Control, Dec. 1983, pp. 410-411.
-
And A.L. Tits, "Nonuniform, Dynamically Adapted Discretization for Functional Constraints in Engineering Design Problems," in Proc.
-
-
Parsa, H.1
-
35
-
-
0015160689
-
-
9, pp. 529-542, 1971.
-
B.C. Eaves and W. I. Zangwill, "Generalized cutting plane algorithms," SIAM J. Control, vol. 9, pp. 529-542, 1971.
-
And W. I. Zangwill, "Generalized Cutting Plane Algorithms," SIAM J. Control, Vol.
-
-
Eaves, B.C.1
-
36
-
-
0032639484
-
-
1999, pp. 945-950.
-
M. Krasnicki, R. Phelps, R.A. Rutenbar, and L. R. Carley, "MAELSTROM: Efficient simulation-based synthesis for custom analog cells," in Proc. IEEE/ACM Design Automation Conf., June 1999, pp. 945-950.
-
R. Phelps, R.A. Rutenbar, and L. R. Carley, "MAELSTROM: Efficient Simulation-based Synthesis for Custom Analog Cells," in Proc. IEEE/ACM Design Automation Conf., June
-
-
Krasnicki, M.1
-
38
-
-
0029304902
-
-
30, pp. 586-590, May 1995.
-
K.-M. Tham and K. Nagaraj, "A low supply voltage high PSRR voltage reference in CMOS process," IEEE J. Solid-State Circuits, vol. 30, pp. 586-590, May 1995.
-
And K. Nagaraj, "A Low Supply Voltage High PSRR Voltage Reference in CMOS Process," IEEE J. Solid-State Circuits, Vol.
-
-
Tham, K.-M.1
-
39
-
-
0024754187
-
-
24, pp. 1433-1439, Oct. 1989.
-
M.J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J Solid-State Circuits, vol. 24, pp. 1433-1439, Oct. 1989.
-
Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching Properties of MOS Transistors," IEEE J Solid-State Circuits, Vol.
-
-
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