A High Performance 0.18 um CMOS Technology Designed for Manufacturability

European Solid-State Device Research Conference

Volumn , Issue , 1997, Pages 404-407

  Badenes, G ^a   Hendriks, M ^b   Perello C ^a   Deferm, L ^a  

^a IMEC   (Belgium)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; HARD DISK STORAGE; LEAKAGE CURRENTS;

CMOS TECHNOLOGY; DRIVE CURRENTS; GATE OXIDE THICKNESS; LATERAL ISOLATION; MANUFACTURABILITY; NMOS TRANSISTORS; PMOS TRANSISTORS; RING OSCILLATOR;

AMORPHOUS SILICON;

EID: 33749981957     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.1997.194451     Document Type: Conference Paper

References (3)

1. G. Badenes, R. Rooyackers, I. De Wolf, L. Deferm, Jpn. J. Appl. Phys., 36, 3B, pp. 1325-1329, (March 1997)
2. M. Rodder, S. Aur, J.C. Hu, I.-C. Chen, IEDM 95 Technical Digest, pp. 415-418 (1995).
3. P. Bouillon, T. Skotnicki, C. Kelaidis, R. Gwoziecki, P. Dollfus, J.-L. Regolini, I. Sagnes, S. Bodnar, IEDM 96 Technical Digest, pp. 559-561 (1996).