Optimisation of critical parameters in a low cost, high performance deep submicron CMOS technology

European Solid-State Device Research Conference

Volumn 13-15 Sept. 1999, Issue , 1999, Pages 628-631

  Badenes, G ^a   Perello, C ^a   Rupp, A ^b   Vandamme, E ^a   Augendre, E ^a   Pochet, S ^a   Deferm, L ^a  

^a IMEC   (Belgium)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; COSTS;

DEEP-SUBMICRON CMOS TECHNOLOGY; GATE OXIDE THICKNESS; HIGH FREQUENCY PERFORMANCE; IMPROVE PERFORMANCE; JUNCTION PROFILES; LOW VOLTAGE OPERATION; SILICON TECHNOLOGIES; TECHNOLOGICAL PARAMETERS;

CMOS INTEGRATED CIRCUITS;

EID: 84907888160     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. The National Technology Roadmap for Semiconductors, 1997 Edition. SIA (1997)
2. G. Badenes . M. Hendriks. C. Perello. L. Deferm. A High Performance 0.18 μ mTechnology Designed for Manufacturability. Proceedings of ESSDERC'97. p. 404 (1997)