High performance raised Gate/Source/Drain transistors for sub-0.15 μm CMOS technologies

European Solid-State Device Research Conference

Volumn 13-15 Sept. 1999, Issue , 1999, Pages 388-391

  Van Meer, H ^a   Kubicek, S ^a   Lyu, J ^a   Caymax, M ^a   Loo, R ^a   De Meyer, K ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS;

CMOS TECHNOLOGY; CMOS TRANSISTORS; EPITAXIAL SILICON; GATE LENGTH; PMOS TRANSISTORS; PROCESS COMPLEXITY; SELECTIVE GROWTH; SOURCE AND DRAINS;

TRANSISTORS;

EID: 84907907198     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. T. Ohguro, H. Naruse, H. Sugaya, S. Nakamura, E. Morifuji, H. Kimima, T. Yoshitomi, T. Morimoto, H. S. Momose, Y. Katsumata and H. Iwai, "High performance RF characteristics of raised gate/source/drain CMOS with Co salicide", VLSI Tech. Dig., 1998.
3. A. Waite, S. Kubicek, D. Howard, M. Caymax, K. De Meyer and A. Evans, "A novel deep submicron elevated source/drain MOSFET", Proceedings of the ESSDERC'98, Bordeaux, pp. 148-151, 1998.
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