Suitability of elevated source/drain for deep submicron CMOS

European Solid-State Device Research Conference

Volumn 13-15 Sept. 1999, Issue , 1999, Pages 384-387

  Gwoziecki, R ^a   Jurczak, M ^b   Skotnicki, T ^a   Regolini, J L ^a   Paoli, M ^a  

^a ORANGE LABS   (France)

^b WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC RESISTANCE;

CURRENT DRIVES; DEEP SUBMICRON CMOS; ELEVATED SOURCE/DRAIN; OFF-STATE LEAKAGE; PMOS DEVICES; SERIES RESISTANCES; SUBSTANTIAL REDUCTION; THIN SPACER;

MOS DEVICES;

EID: 84907895585     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. T. Uchino et al., IEDM97, p. 479.
3. T. Ohguro et al., IEDM98, P. 927.
4. A. Waite et al., ESSDERC98, p. 148.
5. A. Waite et al., ESSDERC97, . p. 256
6. K. Ng, et al. JEEE TED, vol. ED-33, no. 7, 1986, p. 965.