Technology mapping for simultaneous gate and interconnect optimisation

IEE Proceedings: Computers and Digital Techniques

Volumn 146, Issue 1, 1999, Pages 21-31

  Lu, A ^a,b   Stenz, G ^a   Eisenmann, H ^a   Johannes, F M ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ESTIMATION; FUNCTIONS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MATHEMATICAL MODELS; OPTIMIZATION;

DELAY MODEL; POSTPLACEMENT LOGIC RESYNTHESIS; TECHNOLOGY MAPPING;

LOGIC GATES;

EID: 0032670930     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19990245     Document Type: Article

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