Delay and area optimization for compact placement by gate resizing and relocation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn , Issue , 1994, Pages 145-148

  Chuang, Weitong ^a   Hajj, Ibrahim N ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; COMPUTATIONAL COMPLEXITY; DELAY CIRCUITS; FUNCTIONS; INTEGRATED CIRCUIT LAYOUT; LINEAR PROGRAMMING; LOGIC DESIGN; MATHEMATICAL MODELS; OPTIMIZATION;

CONVEX PIECEWISE LINEAR FUNCTION; GATE RESIZING; INTERCONNECT CAPACITANCE; INTRINSIC DELAY; MAPPING ALGORITHM; PATH DELAYS; STANDARD CELL; TIMING DRIVEN PLACEMENT; WORST CASE DELAY;

LOGIC GATES;

EID: 0028714506     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (8)