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Volumn , Issue , 1996, Pages 740-745
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Post-layout optimization for deep submicron design
a
a
NEC CORPORATION
(Japan)
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
BUFFER CIRCUITS;
DELAY CIRCUITS;
DYNAMIC PROGRAMMING;
ELECTRIC NETWORK SYNTHESIS;
ELECTRIC VARIABLES CONTROL;
ELECTRIC WIRING;
GRAPH THEORY;
LOGIC DESIGN;
LOGIC GATES;
OPTIMIZATION;
LOGIC SYNTHESIS;
POST LAYOUT OPTIMIZATION;
INTEGRATED CIRCUIT LAYOUT;
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EID: 0029697004
PISSN: 0738100X
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/240518.240659 Document Type: Conference Paper |
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Times cited : (12)
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References (10)
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