A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 2, 2000, Pages 149-162

  Takai, Yasuhiro ^a   Fujita, Mamoru ^a   Nagata, Kyoichi ^a   Isa, Satoshi ^a   Nakazawa, Shigeyuki ^a   Hirobe, Atsunori ^a   Ohkubo, Hiroaki ^a   Sakao, Masato ^a   Horiba, Shinichi ^a   Fukase, Tadashi ^a   Takaishi, Yoshihiro ^a   Matsuo, Makoto ^a   Komuro, Masahiro ^a   Uchida, Tetsuya ^a   Sakoh, Takashi ^a   Saino, Kanta ^a   Uchiyama, Shirou ^a   Takada, Yuichi ^a   Sekine, Junichi ^b   Nakanishi, Nobuko ^b   Oikawa, Takeshi ^b   Igeta, Masahiko ^b   Tanabe, Hiroyoshi ^a   Miyamoto, Hidenobu ^a   Hashimoto, Takeo ^a   Yamaguchi, Hiromu ^a   Koyama, Kuniaki ^a   Kobayashi, Yasuo ^a   Okuda, Takashi ^a   more..

^a NEC CORPORATION   (Japan)

^b NEC IC Microcomputer Systems Ltd   (Japan)

Author keywords

1 Gb; Clock; Clock generator; Clock synchronization; Delay circuit; Double data rate (DDR); DRAM; Input buffer; Interbank shared redundancy; Low cost; Low voltage; LVCMOS; Receiver; Redundancy; Skew; Synchronous DRAM; TTL

Indexed keywords

CMOS INTEGRATED CIRCUITS; REDUNDANCY; TIMING CIRCUITS;

BIDIRECTIONAL DELAY (BDD); DOUBLE DATA RATE (DDR); INTERBANK SHARED REDUNDANCY SCHEMES (ISR); SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM); VARIABLE UNIT REDUNDANCY (VUR);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0033895069     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.823441     Document Type: Article

References (14)

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