256 Mbit synchronous DRAM

NEC Research and Development

Volumn 38, Issue 1, 1997, Pages 1-8

  Nagata, Kyoichi ^a   Matano, Tatsuya ^a   Sakaktbara, Kenichi ^b   Miyano, Kazutaka ^b   Hoshino, Yukio ^b   Isa, Satoshi ^a   Nakazawa, Shigeyuki ^a  

^a ULSI Device Development Laboratories   (Japan)

^b First Memory Division

Author keywords

DRAM; Flexible row redundancy; Pipeline; Prefetch; SMD (Synchronous Mirror Delay); Synchronous; Word driver

Indexed keywords

SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY; SYNCHRONOUS MIRROR DELAY (SMD);

DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LSI CIRCUITS; MOS DEVICES; PIPELINE PROCESSING SYSTEMS; REDUNDANCY;

RANDOM ACCESS STORAGE;

EID: 0343682793     PISSN: 0547051X     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (5)

1. Y. Kodama, et al., "A 150-MHz 4-Bank 64 M-bit SDRAM with Address Incrementing Pipeline Scheme," 1994 Symp. VLSI Circuits, Dig. Tech. Pap., pp. 81-82, 1994.
2. M. Nakamura, et al., "A 29 ns 64 Mb DRAM with Hierarchical Array Architecture," ISSCC Dig. Tech. Pap., pp. 246-245, Feb. 1995.
3. H. Yoo, et al., "A 150 MHz 8-Banks 256 M Synchronous DRAM with Wave Pipelining Methods," ISSCC Dig. Tech. Pap., pp. 250-251, Feb. 1995.
4. I. A. Young, et al., "A PLL Clock Generator with 5 to 110 MHz Lock Range for Microprocessors," ISSCC Dig. Tech. Pap., pp. 50-51, Feb. 1992.
5. T. Lee, et al., "A 2.5 V DLL for an 18 Mb, 500 MB/sec DRAM," ISSCC Dig. Tech. Pap., pp. 300-301, Feb. 1994.