On-chip timing adjuster with sub-100-ps resolution for a high-speed DRAM interface

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1998, Pages 62-63

  Noda, Hiromasa ^a   Aoki, Masakazu ^a   Tanaka, Hitoshi ^a   Nagashima, Osamu ^a   Aoki, Hideyuki ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; ERROR ANALYSIS; INTEGRATED CIRCUIT LAYOUT;

TIMING ADJUSTERS;

DELAY CIRCUITS;

EID: 0031631230     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)